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74F8965 Fiches technique(PDF) 1 Page - NXP Semiconductors |
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74F8965 Fiches technique(HTML) 1 Page - NXP Semiconductors |
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1 / 11 page  Philips Semiconductors FAST Products Product specification 74F8965/74F8966 9-Bit address/data Futurebus transceiver, ADT 1 December 19, 1990 853 1526 01320 FEATURES • 9–bit transceiver (both directions) • Drives heavily loaded backplanes with equivalent load impedances down to 10 ohms • High drive (100mA) open collector drivers on B port • Reduced voltage swing (1V to 2V) produces less noise and reduces power consumption • High speed operation enhances performance of backplane buses and facilitates incident wave switching • Compatible with IEEE 896 futurebus standards and IEEE 1194 BTL stan- dard • Built–in precision band–gap reference provides accurate receiver thresholds and improved noise immunity • Controlled output ramp and multiple GND pins minimize ground bounce • Glitch–free power up/power down operation • Guaranteed skew of less than 2ns DESCRIPTION The 74F8965 and 74F8966 are 9–bit bidirectional latchable transceivers and are intended to provide the electrical interface to a high performance wired–OR bus. The B port inverting drivers are low–capacitance open collector with controlled ramp and are designed to sink 100mA from 2 volts. The B port inverting receivers have a precision band gap references for improved noise margins. The B port interfaces to ’Backplane Transceiver Logic’ (BTL). BTL features a reduced (1V to 2V) voltage swing for lower power consumption and a series diode on the drivers to reduce capacitive loading. Incident wave switching is employed, there- fore BTL propagation delays are short. Al- though the voltage swing is much less for BTL, so is its receiver threshold region, therefore noise margins are excellent. BTL offers low power consumption, low ground bounce, EMI and crosstalk, low capacitive loading, superior noise margin and low propagation delays. This results in a high bandwidth, reliable backplane. The 74F8965 and 74F8966 A ports have TTL 3–state drivers and TTL receivers. The B ports have standard BTL I/O with 100mA current sink capability. The B–to–A path is a simple inverted buffered path. When going from A–to–B the user may choose be- tween a buffered path or a latching function. The 74F8966 also has an idle arbitrator/multi- ple competitors output. The IAMC output compares, using a wired–OR configuration, the data on the bus to the latched data pres- ented to the bus. If the bus data matches the data presented by the 74F8966 then IAMC is high. If the data doesn’t match then IAMC goes low. TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT( TOTAL) 74F8965 3.5ns 80mA 74F8966 3.5ns 80mA ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 44–pin PLCC N74F8965A, N74F8966A INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW A0 – A8 TTL data inputs 1.0/0.033 20 µA/20µA B0 – B8 Data inputs with threshold circuitry 5.0/0.167 100 µA/100µA OEA, OEB0, OEB1 Output enable inputs 1.0/0.167 20 µA/100µA LS Latch select (active low) (’F8965) 1.0/0.167 20 µA/100µA IAREQ Idle arbitration request (active low) (’F8965) 1.0/0.167 20 µA/100µA LE Latch enable input (active low) 1.0/0.167 20 µA/100µA A0 – A8 3–state TTL outputs 150/40 3mA/24mA B0 – B8 Open collector BTL outputs OC/166.7 OC/100mA IAMC Idle arbitration/multiple competitors output (’F8966) OC/80 OC/48mA Notes to input and output loading and fan out table 1. One (1.0) FAST unit load is defined as: 20 µA in the high state and 0.6mA in the low state. 2. OC = Open collector. |
Numéro de pièce similaire - 74F8965 |
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Description similaire - 74F8965 |
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