Philips Semiconductors

Product specification

74F50109

Synchronizing dual J–K positive edge-triggered

flip-flop with metastable immune characteristics

September 14, 1990

3

LOGIC DIAGRAM

GND = Pin 8

K

Q

Q

CP

4, 12

3, 13

6, 10

7, 9

SF00601

1, 15

5, 11

RD

SD

J

2, 14

DESCRIPTION

The 74F50109 is a dual positive edge-triggered JK-type flip-flop

featuring individual J, K, clock, set, and reset inputs; also true and

complementary outputs.

Set (SD) and reset (RD) are asynchronous active low inputs and

operate independently of the clock (CP) input.

The J and K are edge–triggered inputs which control the state

changes of the flip–flops as described in the function table.

The J and K inputs must be stable just one setup time prior to the

low–to–high transition of the clock for guaranteed propagation

delays. The JK design allows operation as a D flip–flop by tying J

and K inputs together.

The 74F50109 is designed so that the outputs can never display a

metastable state due to setup and hold time violations. If setup time

and hold time are violated the propagation delays may be extended

beyond the specifications but the outputs will not glitch or display a

metastable state. Typical metastability parameters for the 74F50109

are:

of the rate at which a latch in a metastable state resolves that

propensity of a latch to enter a metastable state.

METASTABLE IMMUNE CHARACTERISTICS

Philips Semiconductors uses the term ’metastable immune’ to

describe characteristics of some of the products in its FAST family.

Specifically the 74F50XXX family presently consist of 4 products

which displays metastable immune characteristics. This term means

that the outputs will not glitch or display an output anomaly under

any circumstances including setup and hold time violations.

This claim is easily verified on the 74F5074. By running two

independent signal generators (see Fig. 1) at nearly the same

frequency (in this case 10MHz clock and 10.02 MHz data) the

device–under–test can be often be driven into a metastable state. If

the Q output is then used to trigger a digital scope set to infinite

persistence the Q output will build a waveform.0 An experiment was

run by continuously operating the devices in the region where

metastability will occur.

When the device–under–test is a 74F74 (which was not designed

with metastable immune characteristics) the waveform will appear

as in Fig. 2.

Fig. 2 shows clearly that the Q output can vary in time with respect

to the Q trigger point. This also implies that the Q or Q output

waveshapes may be distorted. This can be verified on an analog

scope with a charge plate CRT. Perhaps of even greater interest are

the dots running along the 3.5V volt line in the upper right hand

quadrant. These show that the Q output did not change state even

though the Q output glitched to at least 1.5 volts, the trigger point of

the scope.

When the device–under–test is a metastable immune part, such as

the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q

output will appear as in Fig. 3. The 74F5074 Q output will not vary

with respect to the Q trigger point even when the a part is driven into

a metastable state. Any tendency towards internal metastability is

resolved by Philips Semiconductors patented circuitry. If a

metastable event occurs within the flop the only outward

manifestation of the event will be an increased clock–to–Q/Q

propagation delay. This propagation delay is, of course, a function of

the metastability characteristics of the part defined by

The metastability characteristics of the 74F5074 and related part

types represent state–of–the–art TTL technology.

between failures (MTBF) is simple. Suppose a designer wants to

use the 74F50729 for synchronizing asynchronous data that is

arriving at 10MHz (as measured by a frequency counter), has a

clock frequency of 50MHz, and has decided that he would like to

sample the output of the 74F50109 10 nanoseconds after the clock

edge. He simply plugs his number into the equation below:

input event frequency, and t’ is the time after the clock pulse that the

output is sampled (t’ < h, h being the normal propagation delay). In

because input events consist of both of low and high transitions.

DQ

Q

CP

TRIGGER

DIGITAL

SCOPE

INPUT

SIGNAL GENERATOR

SF00586

SIGNAL GENERATOR

Figure 1. Test setup