Philips Semiconductors

Product specification

74F193

Up/down binary counter with separate up/down clocks

2

1995 Jul 17

853-0353 15459

FEATURES

DESCRIPTION

The 74F193 is a 4-bit synchronous up/down counter in the binary

simplify operation. The outputs change state synchronously with the

device can be cleared at any time by the asynchronous reset pin. It

may also be loaded in parallel by activating the asynchronous

parallel load pin.

Inside the device are four master-slave JK flip-flops with the

necessary steering logic to provide the asynchronous reset,

asynchronous preset, load, and synchronous count up and count

down functions.

Each flip-flop contains JK feedback from slave to master, such that a

count by one.

One clock should be held High while counting with the other,

because the circuit will either count by twos or not at all, depending

on the state of the first JK flip-flop, which cannot toggle as long as

either clock input is Low. Applications requiring reversible operation

must make the reversing decision while the activating clock is High

to avoid erroneous counts.

outputs are normally High. When the circuit has reached the

again, duplicating the count up clock, although delayed by two gate

as the clock input signals to the next higher order circuit in a

multistage counter, since they duplicate the clock waveforms.

Multistage counters will not be fully synchronous since there is a

two-gate delay time difference added for each stage that is added.

The counter may be preset by the asynchronous parallel load

capability of the circuit. Information present on the parallel Data

inputs (D0 - D3) is loaded into the counter and appears on the

outputs regardless of the conditions of the clock inputs when the

Parallel Load (PL) input is Low. A High level on the Master Reset

(MR) input will disable the parallel load gates, override both clock

inputs, and set all Q outputs Low. If one of the clock inputs is Low

during and after a reset or load operation, the next Low-to-High

transition of the clock will be interpreted as a legitimate signal and

will be counted.

TYPE

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F193

125MHz

32mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

PKG DWG #

16-pin plastic DIP

N74F193N

SOT38-4

16-pin plastic SO

N74F193D

SOT109-1

PIN CONFIGURATION

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

D1

Q1

Q0

CPD

CPU

Q2

Q3

D0

TCD

TCU

D2

D3

PL

GND

MR

VCC

SF00745

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F(U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

D0 - D3

Data inputs

1.0/1.0

20

µA/0.6mA

Count up clock input (active rising edge)

1.0/3.0

20

µA/1.8mA

Count down clock input (active rising edge)

1.0/3.0

20

µA/1.8mA

PL

Asynchronous parallel load control input (active Low)

1.0/1.0

20

µA/0.6mA

MR

Asynchronous master reset input

1.0/1.0

20

µA/0.6mA

Q0 - Q3

Flip-flop outputs

50/33

1.0mA/20mA

Terminal count up (carry) output (active Low)

50/33

1.0mA/20mA

Terminal count down (borrow) output (active Low)

50/33

1.0mA/20mA

NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20

µA in the High state and 0.6mA in the Low state.