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74ALVT162821 Fiches technique(PDF) 2 Page - NXP Semiconductors

No de pièce 74ALVT162821
Description  2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger with 30ohm termination resistors 3-State
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Fabricant  PHILIPS [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74ALVT162821 Fiches technique(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74ALVT162821
2.5V/3.3V 20-bit bus-interface D-type flip-flop;
positive-edge trigger with 30
W termination resistors (3-State)
2
1998 Oct 02
853-2041 20127
FEATURES
Outputs include series resistance of 30W making external
termination resistors unnecessary
20-bit positive-edge triggered register
5V I/O Compatible
Multiple V
CC and GND pins minimize switching noise
Live insertion/extraction permitted
Power-up reset
Power-up 3-State
Output capability +12mA/-12mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
Bus hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
DESCRIPTION
The 74ALVT162821 high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive. It is designed for VCC operation at 2.5V or 3.3V with I/O
compatibility to 5V.
The 74ALVT162821 has two 10-bit, edge triggered registers, with
each register coupled to a 3-State output buffer. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active Low Output Enable (nOE) controls all ten 3-State buffers
independent of the register operation. When nOE is Low, the data in
the register appears at the outputs. When nOE is High, the outputs
are in high impedance “off” state, which means they will neither drive
nor load the bus.
The 74ALVT162821 is designed with 30
W series resistance in both
High and Low output stages. This design reduces the line noise in
applications such as memory address drivers, clock drivers and bus
receivers/transmitters. The series termination resistors reduce
overshoot and undershoot and are ideal for driving memory arrays.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
SYMBOL
PARAMETER
Tamb = 25°C
2.5V
3.3V
UNIT
tPLH
tPHL
Propagation delay
nCP to nQ
CL = 50pF
4.4
3.8
3.2
3.2
ns
CIN
Input capacitance
VI = 0V or VCC
3
3
pF
COUT
Output capacitance
VO = 0 or VCC
9
9
pF
ICCZ
Total supply current
Outputs disabled
40
70
µA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
–40
°C to +85°C
74ALVT162821 DL
AV162821 DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40
°C to +85°C
74ALVT162821 DGG
AV162821 DGG
SOT364-1


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