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74ALS138D Fiches technique(PDF) 2 Page - NXP Semiconductors

No de pièce 74ALS138D
Description  1-of-8 decoder/demultiplexer
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Fabricant  PHILIPS [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74ALS138D Fiches technique(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74ALS138
1-of-8 decoder/demultiplexer
2
1996 Jul 03
853–1848 17016
FEATURES
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
DESCRIPTION
The 74ALS138 decoder accepts three binary weighted inputs (A0,
A1, A2) and when enabled, provides eight mutually exclusive,
active-Low outputs (Q0 – Q7). The device features three Enable
inputs; two active-Low (E0, E1) and one active-High (E2). Every
output will be High unless E0 and E1 are Low and E2 is High. This
multiple enable function allows easy parallel expansion of the device
to 1-of-32 (5 lines to 32 lines) decoder with just four 74ALS138s and
one inverter. The device can be used as an eight output
demultiplexer by using one of the active-Low Enable inputs as the
data input and the remaining Enable inputs as strobes. Enable
inputs not used must be permanently tied to their appropriate
active-High or active-Low state.
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74ALS138
12.0ns
4.0mA
PIN CONFIGURATION
16
15
14
13
12
11
10
7
6
5
4
3
2
1
Q7
VCC
Q3
Q4
Q5
Q2
Q0
Q1
A0
A1
E2
A2
E0
E1
9
8
GND
Q6
SF00174
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
DRAWING
NUMBER
16-pin plastic DIP
74ALS138N
SOT38-4
16-pin plastic SO
74ALS138D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0 – A2
Address inputs
1.0/1.0
20
µA/0.1mA
E0, E1
Enable inputs (active-Low)
1.0/1.0
20
µA/0.1mA
E2
Enable input (active-High)
1.0/1.0
20
µA/0.1mA
Q0 – Q7
Data outputs (active-Low)
50/33
1.0mA/20mA
NOTE:
One (1.0) ALS unit load is defined as: 20
µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
A1 A2
A0
Q2 Q3 Q4 Q5
13 12 11 10
12
3
VCC = Pin 16
GND = Pin 8
SF00175
Q1
14
Q0
15
Q6
9
Q7
7
4
5
6
E0
E1
E2
IEC/IEEE SYMBOL
SC00047
DX
1
2
4
5
6
15
14
13
12
11
10
9
7
0
0
1
2
G
0
7
3
3
2
&


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