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74AHCT595 Fiches technique(PDF) 11 Page - NXP Semiconductors |
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74AHCT595 Fiches technique(HTML) 11 Page - NXP Semiconductors |
11 / 20 page 2000 Mar 15 11 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74AHC595; 74AHCT595 Notes 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5.0 V. VCC = 4.5 to 5.5 V; note 2 tPHL/tPLH propagation delay SHCP to Q7’ see Figs 7 and 12 15 pF − 4.0 8.2 1.0 9.4 1.0 10.5 ns propagation delay STCP to Qn see Figs 8 and 12 − 4.2 7.4 1.0 8.5 1.0 9.5 ns tPHL propagation delay MR to Q7’ see Figs 10 and 12 − 4.4 8.0 1.0 9.1 1.0 10.0 ns tPZH/tPZL 3-state output enable time OE to Qn see Figs 11 and 12 − 4.0 8.6 1.0 10.0 1.0 11.0 ns tPHZ/tPLZ 3-state output disable time OE to Qn − 3.8 8.0 1.0 9.5 1.0 10.5 ns tPHL/tPLH propagation delay SHCP to Q7’ see Figs 7 and 12 50 pF − 5.4 10.0 1.0 11.4 1.0 12.5 ns propagation delay STCP to Qn see Figs 8 and 12 − 5.5 9.0 1.0 10.5 1.0 11.5 ns tPHL propagation delay MR to Q7’ see Figs 10 and 12 − 5.6 10.0 1.0 11.1 1.0 12.0 ns tPZH/tPZL 3-state output enable time OE to Qn see Figs 11 and 12 − 5.3 10.6 1.0 12.0 1.0 13.0 ns tPHZ/tPLZ 3-state output disable time OE to Qn − 5.8 10.3 1.0 11.0 1.0 12.0 ns tW shift clock pulse width HIGH or LOW see Figs 7 and 12 5.0 −− 5.0 − 5.0 − ns storage clock pulse width HIGH or LOW see Figs 8 and 12 5.0 −− 5.0 − 5.0 − ns master reset pulse width LOW see Figs 10 and 12 5.0 −− 5.0 − 5.0 − ns tsu set-up time DS to SHCP see Figs 8 and 12 3.0 −− 3.0 − 3.0 − ns set-up time SHCP to STCP see Figs 9 and 12 5.0 −− 5.0 − 5.0 − ns th hold time DS to SHCP 2.0 −− 2.0 − 2.0 − ns trem removal time MR to SHCP see Figs 10 and 12 2.5 −− 2.5 − 2.5 − ns fmax maximum clock pulse frequency SHCP or STCP see Figs 7, 8 and 12 130 170 − 110 − 90 − MHz SYMBOL PARAMETER TEST CONDITIONS Tamb (°C) UNIT WAVEFORMS CL 25 −40 to +85 −40 to +125 MIN. TYP. MAX. MIN. MAX. MIN. MAX. |
Numéro de pièce similaire - 74AHCT595 |
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Description similaire - 74AHCT595 |
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