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CDMPC823D Fiches technique(PDF) 8 Page - Motorola, Inc |
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CDMPC823D Fiches technique(HTML) 8 Page - Motorola, Inc |
8 / 12 page 8 MPC823e Mobile Computing Microprocessor MOTOROLA Embedded PowerPC Core The PowerPC core complies with standard PowerPC architecture. It has a fully static design that consists of an integer block, hardware multiplier/divider block and a load/store block. The core supports integer operations on a 32-bit internal data path and 32-bit arithmetic hardware. Its interface to the internal and external buses is 32 bits. The core uses a two-instruction load/store queue, four-instruction prefetch queue, and a six-instruction history buffer. It performs branch folding and branch prediction with conditional prefetch, but without conditional execution. With single bus cycles, the core can operate on 32-bit external operands and with critical-word-first in multiple bus cycles. The PowerPC integer block supports 32 x 32-bit fixed-point general-purpose registers and can execute one integer instruction per clock cycle. The PowerPC core is integrated with the memory management units, an instruction cache, and a data cache. The memory management units provide 32-entry, fully associative instruction and data TLBs, with multiple page sizes of 4K (1K protection), 16K, 512K, and 8M. They support 16 virtual address spaces and 16 protection groups. Special registers are available to support software tablewalk and update. The instruction cache is 16K, four-way, set-associative with physical addressing. It allows single-cycle accesses on hit with no added latency for miss. It is four words per line and supports burst line fill using an LRU replacement algorithm. The cache can be locked on a line basis for application critical routines. The data cache is 8K, two-way, set-associative with physical addressing. It allows single-cycle accesses on hit with one added clock latency for miss. It has four words per line and supports burst line fill using an LRU replacement algorithm. The cache can be locked on a line basis for application critical data and can be programmed to support copyback or writethrough mode via the memory management unit. The cache-inhibit mode can be programmed per MMU page. The PowerPC core, with its instruction and data caches, can deliver approximately 99MIPS at 75MHz (using Dhrystone 2.1) or 172K Dhrystones, based on the assumption that it is issuing one instruction per cycle with a cache hit rate of 94%. Communication Processor Module The communication processor module contains features that allow the MPC823 microprocessor to excel in imaging, personal communication, and low-power applications. These features are divided into three categories: • DSP processing • Communication processing • Twelve serial DMA channels and two independent DMA channels The MPC823e embedded DSP function allows the communication processor module to execute imaging algorithms in parallel with the PowerPC core to achieve maximum performance with very little power. The DSP can execute one 16x16 MAC on every clock cycle. It has preprogrammed filtering functions like FIR, MOD, DEMOD, IIR, and downloadable imaging functions for JPEG image compression and decompression. The robust communication features of the MPC823e are provided by the communication processor module. These features include a RISC microcontroller with multiply accumulate hardware, two serial communication controllers, two serial management controllers, one dedicated serial channel for the Universal Serial Bus, one inter-integrated circuit port, one serial peripheral interface, an 8K dual-port RAM, interrupt controller, two time-slot assigners, and four independent baud rate generators. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
Numéro de pièce similaire - CDMPC823D |
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Description similaire - CDMPC823D |
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