74AHCT02PW datasheet(2/16 Pages) PHILIPS

No de pièce	74AHCT02PW

Description	Quad 2-input NOR gate

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Fabricant	PHILIPS [NXP Semiconductors]

Site Internet	http://www.nxp.com

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1999 Sep 23

2

Philips Semiconductors

Product speciﬁcation

Quad 2-input NOR gate

74AHC02; 74AHCT02

FEATURES

• ESD protection:

HBM EIA/JESD22-A114-A

exceeds 2000 V

MM EIA/JESD22-A115-A

exceeds 200 V

CDM EIA/JESD22-C101

exceeds 1000 V

• Balanced propagation delays

• All inputs have Schmitt-trigger

actions

• Inputs accepts voltages higher than

VCC

• For AHC only:

operates with CMOS input levels

• For AHCT only:

operates with TTL input levels

• Specified from

−40 to +85 and +125 °C.

DESCRIPTION

The 74AHC/AHCT02 are high-speed

Si-gate CMOS devices and are pin

compatible with low power Schottky

TTL (LSTTL). They are specified in

compliance with JEDEC standard

No. 7A.

The 74AHC/AHCT02 provides the

Quad 2-input OR function.

FUNCTION TABLE

See note 1.

Note

1. H = HIGH voltage level;

L = LOW voltage level.

INPUT

OUTPUT

nA

nB

nY

LL

H

LHL

HL

L

HH

L

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns.

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

∑ (CL × VCC2 × fo) = sum of outputs;

CL = output load capacitance in pF;

VCC = supply voltage in Volts.

2. The condition is VI = GND to VCC.

PINNING

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

AHC

AHCT

tPHL/tPLH

propagation delay

nA, nB to nY

CL = 15 pF;

VCC =5V

2.9

3.8

ns

CI

input capacitance

VI =VCC or GND 3.0

3.0

pF

CO

output capacitance

4.0

pF

CPD

power dissipation

capacitance

CL = 50 pF;

f = 1 MHz;

notes 1 and 2

7.0

8.0

pF

SYMBOL

DESCRIPTION

1, 4, 10 and 13

1Y to 4Y

data outputs

2, 5, 8 and 11

1A to 4A

data inputs

3, 6, 9 and 12

1B to 4B

data inputs

7

GND

ground (0 V)

14

VCC

DC supply voltage

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