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GS88418B-200 Fiches technique(PDF) 6 Page - GSI Technology |
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GS88418B-200 Fiches technique(HTML) 6 Page - GSI Technology |
6 / 25 page Rev: 1.05 10/2001 6/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88418/36B-200/180/166/150/133 Note: There are pull-up devices on the LBO, ZQ, SCD, and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above table. Enable / Disable Parity I/O Pins This SRAM allows the user to configure the device to operate in Parity I/O active (x18 or x36) or in Parity I/O inactive (x16 or x32) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Tying PE high deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits generated and read into the ByteSafe parity circuits. Burst Counter Sequences BPR 1999.05.18 Mode Pin Functions Mode Name Pin Name State Function Burst Order Control LBO L Linear Burst H or NC Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, IDD = ISB Single/Dual Cycle Deselect Control SCD L Dual Cycle Deselect H or NC Single Cycle Deselect FLXDrive Output Impedance Control ZQ L High Drive (Low Impedance) H Low Drive (High Impedance) Linear Burst Sequence Note: The burst counter wraps to initial state on the 5th clock. Interleaved Burst Sequence Note: The burst counter wraps to initial state on the 5th clock. A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 |
Numéro de pièce similaire - GS88418B-200 |
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Description similaire - GS88418B-200 |
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