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GS88118BT Fiches technique(PDF) 11 Page - GSI Technology

No de pièce GS88118BT
Description  512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
Download  39 Pages
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Fabricant  GSI [GSI Technology]
Site Internet  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS88118BT Fiches technique(HTML) 11 Page - GSI Technology

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Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/2005
11/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in
the default states as specified in the above tables.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Burst Counter Sequences
BPR 1999.05.18


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