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GS881E32BGD-200I Fiches technique(PDF) 11 Page - GSI Technology

No de pièce GS881E32BGD-200I
Description  512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
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Fabricant  GSI [GSI Technology]
Site Internet  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS881E32BGD-200I Fiches technique(HTML) 11 Page - GSI Technology

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GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Rev: 1.04 3/2005
11/40
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Note:
There is a pull-up device onthe FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in
the default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
FLXDrive Output Impedance Control
ZQ
L
High Drive (Low Impedance)
H or NC
Low Drive (High Impedance)
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00


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