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GS8170DD36C-333I Fiches technique(PDF) 11 Page - GSI Technology |
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GS8170DD36C-333I Fiches technique(HTML) 11 Page - GSI Technology |
11 / 29 page GS8170DD36C-333/300/250/200 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 2.03 1/2005 11/29 © 2002, GSI Technology, Inc. CMOS Output Driver Impedance Control CMOS I/O SigmaRAMs are supplied with selectable (high or low) impedance output drivers. The ZQ pin allows selection between SRAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ high) point-to-point applications. SigmaRAM DDR Bank Switch with E1 Deselect QA0 QA1 QC0 QC1 QD0 QD1 Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false. F /E2 Bank 1 E2 Bank 2 DQ Bank 1 /E1 C ADV Read D Read DQ Bank 2 CQ Bank 1 CQ1 + CQ2 Read CQ Bank 2 CK E Read No Op Address A XX |
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