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74ABTH16373BDGG Fiches technique(PDF) 7 Page - NXP Semiconductors |
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74ABTH16373BDGG Fiches technique(HTML) 7 Page - NXP Semiconductors |
7 / 10 page Philips Semiconductors Product specification 74ABT16373B 74ABTH16373B 16-bit transparent latch (3-State) 1998 Feb 27 7 NOTE: The shaded areas indicate when the input is per- mitted to change for predictable output performance. VM nDx VM VM VM VM nE ts(H) th(H) ts(L) th(L) SA00049 VM Waveform 3. Data Setup and Hold Times nOE VM tPZH tPHZ 0V nQx VM VM SA00050 VOH VOH – 0.3V Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level nOE tPZL tPLZ nQx VM VM VM SA00051 VOL + 0.3V VOL Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level TEST CIRCUIT AND WAVEFORM PULSE GENERATOR RT VIN D.U.T. VOUT RL VCC RL 7.0V Test Circuit for 3-State Outputs VM VM tW AMP (V) NEGATIVE PULSE 10% 10% 90% 90% 0V VM VM tW AMP (V) POSITIVE PULSE 90% 90% 10% 10% 0V tTHL (tF) tTLH (tR)tTHL (tF) tTLH (tR) VM = 1.5V Input Pulse Definition DEFINITIONS RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS FAMILY Amplitude Rep. Rate tW tR tF 74ABT/H16 3.0V 1MHz 500ns 2.5ns 2.5ns SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open SA00018 CL |
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