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ADF7025BCPZ-RL Fiches technique(PDF) 10 Page - Analog Devices |
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ADF7025BCPZ-RL Fiches technique(HTML) 10 Page - Analog Devices |
10 / 44 page ADF7025 Rev. A | Page 10 of 44 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 36 35 34 33 32 31 30 29 28 27 26 25 ADF7025 TOP VIEW (Not to Scale) VCOIN VREG1 VDD1 RFOUT RFGND RFIN RFINB RLNA VDD4 RSET VREG4 GND4 CLKOUT DATA CLK DATA I/O INT/LOCK VDD2 VREG2 ADCIN GND2 SCLK SREAD SDATA SLE 1 2 3 4 5 6 7 8 9 10 11 12 PIN 1 INDICATOR Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 VCOIN The tuning voltage on this pin determines the output frequency of the voltage-controlled oscillator (VCO). The higher the tuning voltage, the higher the output frequency. 2 VREG1 Regulator Voltage for PA Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. 3 VDD1 Voltage Supply for PA Block. Decoupling capacitors of 0.1 µF and 10 pF should be placed as close as possible to this pin. All VDD pins should be tied together. 4 RFOUT The modulated signal is available at this pin. Output power levels are from −20 dBm to +13 dBm. The output should be impedance-matched to the desired load using suitable components. See the Transmitter section. 5 RFGND Ground for Output Stage of Transmitter. 6 RFIN LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA input to ensure maximum power transfer. See the LNA/PA Matching section. 7 RFINB Complementary LNA Input. See the LNA/PA Matching section. 8 RLNA External bias resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance. 9 VDD4 Voltage supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor. 10 RSET External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5% tolerance. 11 VREG4 Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND for regulator stability and noise rejection. 12 GND4 Ground for LNA/MIXER Block. 13 to 18 MIX/FILT Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. 19, 22 GND4 Ground for LNA/MIXER Block. 20, 21, 23 FILT/TEST_A Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. 24 CE Chip Enable. Bringing CE low puts the ADF7025 into complete power-down. Register values are lost when CE is low, and the part must be reprogrammed once CE is brought high. 25 SLE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches. A latch is selected using the control bits. 26 SDATA Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high impedance CMOS input. 27 SREAD Serial Data Output. This pin is used to feed readback data from the ADF7025 to the microcontroller. The SCLK input is used to clock each readback bit (ADC readback) from the SREAD pin. 28 SCLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input. |
Numéro de pièce similaire - ADF7025BCPZ-RL |
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Description similaire - ADF7025BCPZ-RL |
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