Moteur de recherche de fiches techniques de composants électroniques |
|
AMD-X5-133AFZ Fiches technique(PDF) 7 Page - Advanced Micro Devices |
|
AMD-X5-133AFZ Fiches technique(HTML) 7 Page - Advanced Micro Devices |
7 / 67 page AMD PRELIMINARY Am5X86 Microprocessor 7 Figure 30 SMM Base Slot Offset ............................................................................................................. 48 Figure 31 SRAM Usage .......................................................................................................................... 48 Figure 32 SMRAM Location .................................................................................................................... 49 Figure 33 SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Through Mode with Caching Enabled During SMM.......................................................................................... 50 Figure 34 SMM Timing in Systems Using Non-Overlaid Memory Spaces and Write-Back Mode with Caching Enabled During SMM ................................................................................................. 50 Figure 35 SMM Timing in Systems Using Non-Overlaid Memory Spaces and Write-Back Mode with Caching Disabled During SMM ................................................................................................ 50 Figure 36 SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode with Caching Enabled During SMM ................................................................................................. 51 Figure 37 SMM Timing in Systems Using Overlaid Memory Spaces and Write-Through Mode with Caching Disabled During SMM ................................................................................................ 51 Figure 38 SMM Timing in Systems Using Overlaid Memory Spaces and Configured in Write-Back Mode...................................................................................................................... 51 Figure 39 CLK Waveforms ...................................................................................................................... 61 Figure 40 Output Valid Delay Timing ...................................................................................................... 61 Figure 41 Maximum Float Delay Timing .................................................................................................. 62 Figure 42 PCHK Valid Delay Timing ....................................................................................................... 62 Figure 43 Input Setup and Hold Timing ................................................................................................... 63 Figure 44 RDY and BRDY Input Setup and Hold Timing ........................................................................ 63 Figure 45 TCK Waveforms ...................................................................................................................... 64 Figure 46 Test Signal Timing Diagram .................................................................................................... 64 LIST OF TABLES Table 1 Clocking Options ....................................................................................................................... 1 Table 2 EADS Sample Time ................................................................................................................ 14 Table 3 Cache Line Organization ......................................................................................................... 19 Table 4 Legal Cache Line States ......................................................................................................... 19 Table 5 MESI Cache Line Status ......................................................................................................... 20 Table 6 Key to Switching Waveforms ................................................................................................... 22 Table 7 WBINVD/INVD Special Bus Cycles ......................................................................................... 33 Table 8 FLUSH Special Bus Cycles ..................................................................................................... 34 Table 9 Pin State during Stop Grant Bus State .................................................................................... 37 Table 10 SMRAM State Save Map ........................................................................................................ 43 Table 11 SMM Initial CPU Core Register Settings ................................................................................. 45 Table 12 Segment Register Initial States ............................................................................................... 45 Table 13 SMM Revision Identifier .......................................................................................................... 46 Table 14 SMM Revision Identifier Bit Definitions ................................................................................... 46 Table 15 HALT Auto Restart Configuration ............................................................................................ 47 Table 16 I/O Trap Word Configuration ................................................................................................... 47 Table 17 Test Register TR4 Bit Descriptions ......................................................................................... 53 Table 18 Test Register TR5 Bit Descriptions ......................................................................................... 53 Table 19 CPU ID Codes ......................................................................................................................... 56 Table 20 CPUID Instruction Description ................................................................................................. 56 Table 21 Thermal Resistance (°C/W) θ JC and θJA for the Am5 X86 CPU in 168-Pin PGA Package ....... 65 Table 22 Maximum T A at Various Airflows in °C .................................................................................... 65 Table 23 Maximum T A for SQFP Package by Clock Frequency ............................................................. 65 |
Numéro de pièce similaire - AMD-X5-133AFZ |
|
Description similaire - AMD-X5-133AFZ |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |