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TSI-4 Fiches technique(PDF) 3 Page - Agere Systems |
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TSI-4 Fiches technique(HTML) 3 Page - Agere Systems |
3 / 61 page Data Sheet, Revision 3 TSI-4 September 21, 2005 4k x 4k Time-Slot Interchanger Table of Contents (continued) Contents Page Agere Systems Inc. 3 Table 2-1. Package Ball Assignments in Signal Name Order.................................................................................................8 Table 2-2. Package Ball Assignments (Top View) ................................................................................................................10 Table 2-3. Package Ball Assignments (Bottom View)........................................................................................................... 11 Table 2-4. Ball Types ............................................................................................................................................................12 Table 2-5. Timing Port ..........................................................................................................................................................12 Table 2-6. Transmit and Receive Concentration Highways ..................................................................................................12 Table 2-7. Control Port..........................................................................................................................................................13 Table 2-8. Initialization and Test Access...............................................................................................................................13 Table 2-9. Power Balls..........................................................................................................................................................14 Table 3-1. Absolute Maximum Ratings .................................................................................................................................15 Table 3-2. Operating Conditions ...........................................................................................................................................15 Table 3-3. ESD Tolerance.....................................................................................................................................................15 Table 3-4. Thermal Parameter Values ..................................................................................................................................16 Table 3-5. Power Consumption ............................................................................................................................................17 Table 4-1. CMOS Inputs .......................................................................................................................................................18 Table 4-2. CMOS Outputs ....................................................................................................................................................18 Table 4-3. CMOS Bidirectionals (DATA[15:0]) ......................................................................................................................18 Table 5-1. CHICLK Timing Specifications .............................................................................................................................19 Table 5-2. MPUCLK Timing Specifications ...........................................................................................................................19 Table 5-3. CMOS Output ac Timing Specification * ..............................................................................................................20 Table 5-4. CHI Interface Timing ............................................................................................................................................21 Table 5-5. CHI 3-State Output Control..................................................................................................................................27 Table 5-6. Microprocessor Port Timing—Read Cycle...........................................................................................................28 Table 5-7. Microprocessor Port Timing—Write Cycle ...........................................................................................................29 Table 6-1. Address Map........................................................................................................................................................31 Table 6-2. Global Registers ..................................................................................................................................................32 Table 6-3. Connection Store Generator Registers................................................................................................................32 Table 6-4. Test Pattern Generator and Monitor Registers ....................................................................................................33 Table 6-5. Concentration Highway Configuration Registers .................................................................................................33 Table 6-6. Switch Fabric Control...........................................................................................................................................33 Table 6-7. Connection Store .................................................................................................................................................34 Table 6-8. Reserved Registers .............................................................................................................................................34 Table 6-9. Version_Control (Read Only)...............................................................................................................................34 Table 6-10. Chip_Identity (Read Only) .................................................................................................................................34 Table 6-11. Summary_Interrupt_Status (Read Only) ............................................................................................................35 Table 6-12. Summary_Interrupt_Mask (Read/Write) ............................................................................................................35 Table 6-13. CPU_Access_Error (CORWN) ..........................................................................................................................36 Table 6-14. CPU_Access_Error_Mask (Read/Write)............................................................................................................36 Table 6-15. Global_Control (Read/Write) .............................................................................................................................37 Table 6-16. PLL_Control (Read/Write) .................................................................................................................................38 Table 6-17. Power_Control (Read/Write)..............................................................................................................................38 Table 6-18. Invalid_Address_Trap (Read Only)....................................................................................................................38 Table 6-19. Scratch_Register (Read/Write) ..........................................................................................................................38 Table 6-20. Reserved_0 (Read/Write) ..................................................................................................................................39 Table 6-21. CSG_Control (Read/Write) ................................................................................................................................39 Table 6-22. CSG_Status (Read Only)...................................................................................................................................40 Table 6-23. CSG_Starting_Address (Read/Write) ................................................................................................................40 Table 6-24. CSG_Ending_Address (Read/Write) .................................................................................................................40 Table 6-25. CSG_Write_Enable_Low (Read/Write)..............................................................................................................40 Table 6-26. CSG_Write_Enable_High (Read/Write).............................................................................................................40 Table 6-27. CSG_Seed_Low (Read/Write)...........................................................................................................................41 Table 6-28. CSG_Seed_High (Read/Write) ..........................................................................................................................41 |
Numéro de pièce similaire - TSI-4 |
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