DM9101
10/100Mbps Ethernet Physical Layer Single Chip Transceiver
Final
5
Version: DM9101-DS-F03
July 22, 1999
Pin Description
Pin No.
Pin Name
I/O
Description
LQFP
QFP
MII Interface
54
56
TX_ER/
TXD4
I
Transmit Error:
In 100Mbps mode, if this signal is asserted high and TX_EN is
active, the HALT symbol is substituted for the actual data nibble.
In 10Mbps mode, this input is ignored.
In bypass modes (BP4B5B or BPALIGN), TX_ER becomes the
TXD4 pin, the fifth TXD data bit.
55-58
57 - 60
TXD3
TXD2
TXD1
TXD0
I
Transmit Data:
Transmit data input pins for nibble data from the MII in 100Mbps
or 10Mbps nibble mode (25 MHz for 100Mbps mode, 2.5MHz for
10Mbps nibble mode).
In 10Mbps serial mode, the TXD0 pin is used as the serial data
input pin. TXD[3:1] are ignored.
61
63
TX_EN
I
Transmit Enable:
Active high input indicates the presence of valid nibble data on
TXD[3:0] for both 100Mbps or 10Mbps nibble mode.
In 10Mbps serial mode, active high indicates the presence of
valid 10Mbps data on TXD0.
62
64
TX_CLK
O,Z
Transmit Clock:
Transmit clock output from the DM9101:
- 25MHz nibble transmit clock derived from transmit Phase
Locked Loop(TX PLL) in 100Base-TX mode
- 2.5MHz transmit clock in 10Base-T nibble mode
- 10MHz transmit clock in 10Base-T serial mode
63
65
MDC
I
Management Data Clock:
Synchronous clock to the MDIO management data input/output
serial interface which is asynchronous to transmit and receive
clocks. The maximum clock rate is 2.5MHz.
64
66
MDIO
I/O
Management Data I/O:
Bi-directional management instruction/data signal that may be
driven by the station management entity or the PHY. This pin
requires a 1.5K
Ω pull-up resistor.
67-70
69 - 72
RXD3
RXD2
RXD1
RXD0
O,Z
Receive Data:
Nibble wide receive data (synchronous to RX_CLK - 25MHz for
100Base-TX mode, 2.5MHz for 10Base-T nibble mode). Data is
driven on the falling edge of RX_CLK.
In 10Mbps serial mode, the RXD0 pin is used as the data output
pin. RXD[3:1] are ignored.
73
75
RX_CLK
O,Z
Receive Clock:
Provides the recovered receive clock for different modes of
operation:
- 25MHz nibble clock in 100Mbps mode
- 2.5MHz nibble clock in 10Mbps nibble mode
- 10MHz receive clock in 10Mbps serial mode
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