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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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EM65568 Fiches technique(PDF) 68 Page - ELAN Microelectronics Corp |
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EM65568 Fiches technique(HTML) 68 Page - ELAN Microelectronics Corp |
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68 / 112 page  EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver * This specification is subject to be changed without notice. 2005/3/8 (V1.2) 68 (At the time of reset: {AY7, AY6, AY5, AY4}=0H, read address: 3H) ※ Mark shows “Don’t care” The AY register set to Y-direction address of display RAM. In data setting, lower place and upper place are divided with 4-bit and 4-bit respectively. 00H to 81H are applicable to the values for AY7 to AY0, and 82H to FFH are not permitted. The address for (AY7 to AY0) = 70H, 81H are in the display RAM area for icon display. 8.2.3 Display Start Address Register (LA) D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 0 0 LA3 LA2 LA1 LA0 0 1 1 0 0 0 0 (At the time of reset: {LA3, LA2, LA1, LA0}=0H, read address: 4H) D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 0 1 ※ LA6 LA5 LA4 0 1 1 0 0 0 0 (At the time of reset: { LA6, LA5, LA4}=0H, read address: 5H) ※ Mark shows “Don’t care” The LA register indicated first output segment data in display RAM. This segment data output to common line indicated by SC register. After that output common line shift to the increment direction. LA6 LA5 LA4 LA3 LA2 LA1 LA0 Line Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ： 1 1 1 1 1 1 1 127 8.2.4 n Line Alternated Register (N) D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 N3 N2 N1 N0 0 1 1 0 0 0 0 (At the time of reset: {N3, N2, N1, N0}=0H, read address: 6H) D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 1 N7 N6 N5 N4 0 1 1 0 0 0 0 (At the time of reset: {N7,N6, N5, N4}=0H, read address: 7H) ※ Mark shows “Don’t care” The reverse line number of LCD alternated drive is required to set in the register. The line number has a limit, must keeps between from 2 to 80 lines. The values set up by the alternated register become enable when NLIN control bit is “1”. When NLIN control bit is “0”, alternated drive waveform reverses by each frame is generated. |
Numéro de pièce similaire - EM65568 |
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Description similaire - EM65568 |
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