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SM16LC05 Fiches technique(PDF) 4 Page - Protek Devices

No de pièce SM16LC05
Description  LOW CAPACITANCE TVS ARRAY
Download  5 Pages
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Fabricant  PROTEC [Protek Devices]
Site Internet  http://www.protekdevices.com
Logo PROTEC - Protek Devices

SM16LC05 Fiches technique(HTML) 4 Page - Protek Devices

  SM16LC05 Datasheet HTML 1Page - Protek Devices SM16LC05 Datasheet HTML 2Page - Protek Devices SM16LC05 Datasheet HTML 3Page - Protek Devices SM16LC05 Datasheet HTML 4Page - Protek Devices SM16LC05 Datasheet HTML 5Page - Protek Devices  
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4
www.protekdevices.com
05051.R10 4/05
SM16LC03
thru
SM16LC36C
APPLICATION NOTE
The SM16LC & SM16LCxxC Series are TVS arrays designed to protect I/O or data lines from the damaging effects of ESD, EFT and other types of
surges. This product series provides both unidiretional and bidirectional protection, with a surge capability of 500 Watts P
PP per line for an 8/20µs
waveform and ESD protection > 40kV.
BIDIRECTIONAL COMMON-MODE CONFIGURATION (Figure 1)
Ideal for RS-485 applications, the SM16LCxxC Series provides up to eight (8) lines of protection in a common-mode configuration as depicted in
Figure 1. This low capacitance series allows the transceiver or telecommunications circuit to operate safely without significant signal distortion.
Circuit connectivity is as follows:
Lines 1 is connected to Pin 9.
Line 2 is connected to Pin 10.
Line 3 is connected to Pin 11.
Line 4 is connected to Pin 12.
Line 5 is connected to Pin 13.
Line 6 is connected to Pin 14.
Line 7 is connected to Pin 15.
Line 8 is connected to Pin 16.
Pins 1-8 are connected to ground.
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Circuit board layout is critical for Electromagnetic Compatibil-
ity (EMC) protection. The following guidelines are recom-
mended:
The protection device should be placed near the input
terminals or connectors, the device will divert the
transient current immediately before it can be coupled
into the nearby traces.
The path length between the TVS device and the
protected line should be minimized.
All conductive loops including power and ground loops
should be minimized.
The transient current return path to ground should be
kept as short as possible to reduce parasitic inductance.
Ground planes should be used whenever possible. For
multilayer PCBs, use ground vias.
Figure 1. Birectional Common-Mode Protection
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
TRANSCEIVER
D
D
R
R
LINE 1
LINE 2
LINE 3
LINE 4
LINE 5
LINE 6
LINE 7
LINE 8


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