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ML671000 Datasheet(Fiches technique) 5 Page - OKI electronic componets

Numéro de pièce ML671000
Description  OKI’s CMOS 32-Bit Single-Chip Microcontroller with Built-in USB Device Controller
Télécharger  25 Pages
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Fabricant  OKI [OKI electronic componets]
Site Internet  http://www.oki.com
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FEDL671000-02
1Semiconductor
ML671000
5/25
PIN DESCRIPTION (1)
Classification
Pin Name
I/O
Function
Description
XA15 to XA1
O
External address bus bits 15 to 1
Address Bus
nLB/XA0
O
Bank 0/1 lower byte select or external address bus bit 0
Data Bus
XD15 to XD0
I/O
External data bus
nCS0
O
Bank 0 chip select signal
nRD
O
Bank 0/1 read enable signal
nR/W
O
Read strobe signal
Bus Control
nWRE/nWRL
O
Bank 0/1 write enable or lower byte write enable signal
OSC0
I
Connection pin for crystal oscillator or ceramic resonator
If an external clock used, input the clock signal to this pin.
OSC1
O
Connection pin for crystal oscillator or ceramic resonator
If an external clock used, leave this pin open (unconnected).
CLKOUT
O
Internal system clock output
PLLEN
I
Enable pin for internal PLL. If PLL is to be used, connect this pin to VDD.
OSCVDD
I
Power supply pin for internal oscillator circuit and PLL. Connect to VDD.
Clock Control
OSCVSS
I—
Power supply pin for internal oscillator circuit and PLL. Connect to
GND.
I/O
Primary
Bit 7 of port 0
P0.7/XA23
O
Secondary
Bit 23 of external address bus
I/O
Primary
Bit 6 of port 0
P0.6/XA22
O
Secondary
Bit 22 of external address bus
I/O
Primary
Bit 5 of port 0
P0.5/XA21
O
Secondary
Bit 21 of external address bus
I/O
Primary
Bit 4 of port 0
P0.4/XA20
O
Secondary
Bit 20 of external address bus
I/O
Primary
Bit 3 of port 0
P0.3/XA19
O
Secondary
Bit 19 of external address bus
I/O
Primary
Bit 2 of port 0
P0.2/XA18
O
Secondary
Bit 18 of external address bus
I/O
Primary
Bit 1 of port 0
P0.1/XA17
O
Secondary
Bit 17 of external address bus
I/O
Primary
Bit 0 of port 0
P0.0/XA16
O
Secondary
Bit 16 of external address bus
I/O
Primary
Bit 7 of port 1
P1.7/nXWAIT
I
Secondary
External wait cycle insert input
I/O
Primary
Bit 6 of port 1
P1.6/nCS1
O
Secondary
Bank 1 chip select signal
I/O
Primary
Bit 5 of port 1
P1.5/nHB/
nWRH
O
Secondary
Bank 0/1 upper byte select or upper byte write enable signal
I/O
Primary
Bit 4 of port 1
P1.4/nRAS1
O
Secondary
Bank 3 row address strobe signal
I/O
Primary
Bit 3 of port 1
P1.3/
nWH/nCASH
O
Secondary
Bank 2/3 upper byte column address strobe signal.
I/O
Primary
Bit 2 of port 1
P1.2/nRAS0
O
Secondary
Bank 2 row address strobe signal
I/O
Primary
Bit 1 of port 1
P1.1/
nCAS/nCASL
O
Secondary
Bank 2/3 column address strobe or lower byte column address strobe
signal
I/O
Primary
Bit 0 of port 1
I/O Ports
P1.0/
nWL/nWE
O
Secondary
Bank 2/3 lower byte write enable or write enable signal




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