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74ABT373CMTCCX Fiches technique(PDF) 2 Page - National Semiconductor (TI) |
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74ABT373CMTCCX Fiches technique(HTML) 2 Page - National Semiconductor (TI) |
2 / 16 page Functional Description The ’ABT373 contains eight D-type latches with TRI-STATE output buffers When the Latch Enable (LE) in- put is HIGH data on the Dn inputs enters the latches In this condition the latches are transparent ie a latch output will change state each time its D input changes When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW tran- sition of LE The TRI-STATE buffers are controlled by the Output Enable (OE) input When OE is LOW the buffers are in the bi-state mode When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches Truth Table Inputs Output LE OE Dn On HL H H HL L L LL X On (no change) XH X Z H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Z e High Impedance State Logic Diagram TLF11547 – 3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 2 |
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