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TC9328AF Fiches technique(PDF) 9 Page - Toshiba Semiconductor |
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TC9328AF Fiches technique(HTML) 9 Page - Toshiba Semiconductor |
9 / 84 page TC9328AF 2002-02-07 9 Pin No. Symbol Pin Name Function and Operation Remarks 48 FMin FM local oscillation signal input 49 AMin AM local oscillation signal input Programmable counter input pin for FM/AM band. For FM input, mode can be switched between 1/2 + Pulse Swallow VHF and FM mode. For AM input, mode can be switched between Pulse Swallow (HF) and Direct Dividing (LF) mode. Normally, local oscillation output (Voltage-Controlled Oscillator: VCO output) of 50 to 230 MHz is input in VHF mode; 30 to 130 MHz in FM mode; 1 to 30 MHz in HF mode; 0.5 to 8 MHz in LF mode. A PLL can be configured using an external prescaller. In such a case, set the pin to LF, and connect the prescaller divider output to the AMin input pin and the PSC input to the P2-3 (PSC) output pin. With an input amp incorporated, capacitive-coupling, small-amplitude operation. Note: The input is at high impedance in PLL Off mode or if the pins are not used for input. 52 51 DO1/P DO2/OT/N Phase comparator output/output port /P output Phase comparator output/output port /N output PLL phase comparator output pins. Tristate output. When the program counter divider output is higher than the reference frequency, H level is output; when lower, L level; and when they match, high impedance. For the phase comparator power supply, a 1.5 V constant voltage supply (Vreg pin) is used. Even if the power supply voltage drops, a stable PLL can be configured. Because DO1 and DO2 are output in parallel, a filter constant can be optimally designed for each FM/AM band. The DO2 pin can be programmed to high impedance or as an output port (OT). Therefore, using the DO1 and DO2 pins, lockup time can be improved or the pins can be effectively used as output ports. Also, the phase comparator charge pump control signal (P/N) can be output from the DO1/2 pin by program so a PLL using an external charge pump can be configured. In such a case, when the program counter divider output is higher than the reference frequency, P/N is output at H/L level; when lower, L/H level; and when they match, L/L level. When set to this mode, H level output becomes VDD level. Note: For tristate output, the H level output uses a constant voltage supply. When H level output current is required, Toshiba recommend using an external power supply. Vreg VDD RfIN1 VDD RfIN2 |
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