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Low Power CMOS SRAM
128K X 16
UC62LS2048
-20/-25
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
AA
t
OH
t
OH
t
RC
ADDRESS
D
OUT
READ CYCLE2
(1,3,4)
t
CE
t
CLZ
(5)
t
CHZ
(5)
CE
D
OUT
READ CYCLE3
(1,4)
t
AA
t
OH
t
RC
ADDRESS
t
CHZ
(5)
CE
D
OUT
OE
t
OHZ
(1,5)
t
OE
t
OLZ
t
BA
t
BE
t
CE
t
CLZ
(5)
t
BDO
UB/LB
NOTES:
1.
WE\ is high in read cycle.
2.
Device is continuously selected when CE\ = VIL
3.
Address valid prior to or coincident with CE\ transition low.
4.
OE\ = VIL.
5.
Transition is measured ±500mV from steady state with CL=5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
U-Chip Technology Corp. LTD.
Preliminary
Rev.1.0
Reserves the right to modify document contents without notice.
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