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PLL620-21 Fiches technique(PDF) 1 Page - PhaseLink Corporation

No de pièce PLL620-21
Description  Low Phase Noise XO (for HF Fund. and 3-rd O.T.)
Download  7 Pages
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Fabricant  PLL [PhaseLink Corporation]
Site Internet  http://www.phaselink.com
Logo PLL - PhaseLink Corporation

PLL620-21 Fiches technique(HTML) 1 Page - PhaseLink Corporation

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Preliminary
PLL620-21
Low Phase Noise XO (for HF Fund. and 3rd O.T.)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
www.phaselink.com Rev 07/15/05 Page 1
FEATURES
• 100MHz to 200MHz Fundamental Mode Crystal.
• Output range: 100 – 200MHz (no multiplication).
• Selectable OE logic.
• Minimum bondwires required for VDD and GND.
• Available outputs: PECL or LVDS.
• Supports 3.3V-Power Supply.
• Available in die form.
• Thickness 10 mil.
DESCRIPTIONS
PLL620-21 is an XO IC specifically designed to work
with high frequency fundamental and third overtone
crystals. Its design was optimized to tolerate higher
limits of interelectrodes capacitance and bonding
capacitance to improve yield. It achieves very low
current into the crystal resulting in better overall
stability. It offers a selectable OE logic and is ideal
for XO applications requiring LVDS or PECL output
levels at high frequencies.
BLOCK DIAGRAM
DIE CONFIGURATION
DIE SPECIFICATIONS
Name
Value
Size
62 x 65 mil
Reverse side
GND
Pad dimensions
80 micron x 80 micron
Thickness
10 mil
OUTPUT SELECTION AND ENABLE
Pad #9
OUTSEL
Selected Output
0
LVDS
1
PECL (default)
Pad #25
OESEL
Pad #30
OE_CTRL
State
0
Tri-state
0
1
Output enabled (default)
0
Output enabled (default)
1
(default)
1
Tri-state
Pad # 9: Bond to GND to set to “0”, bond to VDD to set to “1”
Pad # 30: Logical states defined by PECL levels if OUTSEL (pad # 9) is “1”
Logical states defined by CMOS levels if OUTSEL is “0”
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