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TSB42AC3IPZT Fiches technique(PDF) 9 Page - Texas Instruments |
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TSB42AC3IPZT Fiches technique(HTML) 9 Page - Texas Instruments |
9 / 70 page Overview 3 SLLS593A—January 2006 TSB42AC3 1.5 Terminal Functions PHY Interface D0 − D7 CTL0 CTL1 LPS SCLK DATA0 − DATA31 ADDR0 − ADDR7 CS CA WR INT CYCLEIN CYCLEOUT BCLK RESET EN VCC GND Host Bus 11 18 TSB42AC3 V1.8_reg1 V1.8_reg2 CYST CYDNE GFREMP JTAG_TD1 JTAG_TCK JTAG_TD0 JTAG_RST JTAG_TMS Figure 1−1. TSB42AC3 Terminal Functions Table 1−1. Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION HOST BUS INTERFACE ADDR0−ADDR7 22−25, 27−30 I Host address bus ADDR0 is the most significant bit (MSB). ADDR6 and 7 should be grounded. (Note: FIFO space and configuration registers are quadlet-aligned) CA 35 O Cycle acknowledge (active low). CA is a TSB42AC3 control signal to the host bus. When asserted (low), access to the configuration registers or FIFO is complete. CS 34 I Cycle start (active low). CS is a host bus control signal to indicate the beginning of an access to the TSB42AC3 configuration registers or FIFO space. DATA0−DATA31 82−85, 87−90, 92−95, 97−100, 2−5, 7−10, 12−15, 17−20 I/O Host data bus DATA0 is the most significant bit (MSB). Byte0 (DATA0−DATA7) is the most significant byte. INT 37 O Interrupt (active low). When INT is asserted (low), the TSB42AC3 notifies the host bus that an interrupt has occurred. WR 36 I Read/write enable. When CS is asserted (low) and WR is deasserted (high), a read from the TSB42AC3 is requested by the host bus controller. To request a write access, WR must be asserted (low). BCLK 32 I Host bus clock. BCLK is the clock input supplied by the host to the TSB42AC3. BCLK is asynchronous to the PHY SCLK and supports a maximum frequency of 50 MHz. PHY INTERFACE CTL0, CTL1 63, 62 I/O PHY-link interface control bus. CTL0 and CTL1 indicate the four operations that can occur on this interface (see Section 7 of this document or Annex J of the IEEE 1394−1995 standard for more information about the four operations). D0−D7 60−57, 55−52 I/O PHY-link interface data bus. Data is expected on D0 – D1 for 50/100 Mbits/s packets, D0 – D3 for 200 Mbits/s, and D0 – D7 for 400 Mbits/s. |
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