MC100ES6220 datasheet(5/12 Pages) FREESCALE

No de pièce	MC100ES6220

Description	Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer

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Fabricant	FREESCALE [Freescale Semiconductor, Inc]

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Advanced Clock Drivers Devices

Freescale Semiconductor

5

MC100ES6220

Figure 3. MC100ES6220 AC Test Reference

Figure 4. MC100ES6220 AC Reference Measurement Waveform

Table 6. AC Characteristics (ECL: VEE = –3.3 V ± 5% or VEE = –2.5 V ± 5%, VCC = GND) or

(PECL: VCC = 3.3 V ± 5% or VCC = 2.5 V ± 5%, VEE = GND, TJ = 0°C to +110°C)(1)

1. AC characteristics apply for parallel output termination of 50

Ω to VTT.

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL or ECL differential signals)

VPP

Differential Input Voltage(2) (peak-to-peak)

2. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tPD and

device-to-device skew.

0.3

1.3

V

VCMR

Differential Input Crosspoint Voltage(3)

PECL

ECL

3. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the

VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device

propagation delay, device and part-to-part skew.

1.1

VEE + 1.1

VCC – 0.3

–0.3

V

fCLK

Input Frequency

0

1000

MHz

Differential

PECL/ECL Clock Outputs (QA0-A9, QA0-A9, QB0-B9, QB0-B9)

tPD

Propagation Delay CLKx to Qx0-9

285

550

ps

Differential

VO(P-P)

Differential Output Voltage (peak-to-peak)

400

600

mV

tsk(O)

Output-to-Output Skew

60

130

ps

Differential

tsk(PP)

Output-to-Output Skew (part-to-part)

200

ps

Differential

tJIT(CC)

Output Cycle-to-Cycle Jitter

RMS (1

σ)1

ps

tSK(P)

DCO

Output Pulse Skew(4)

Output Duty Cycle

fREF < 0.1 GHz

fREF < 1.0 GHz

4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH – tpHL |.

49.65

46.5

50

35

50.35

53.5

ps

%

DCREF = 50%

tr, tf

Output Rise/Fall Time

50

350

ps

20% to 80%

Differential Pulse

Generator

Z = 50

Ω

RT = 50 Ω

Z = 50

Ω

DUT

MC100ES6220

VTT

RT = 50 Ω

Z = 50

Ω

VTT

tPD (CLKN to QX)

VCMR = VCC – 1.3 V

VPP = 0.8 V

CLKN

QX

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Description similaire - MC100ES6220

Fabricant	No de pièce	Fiches technique	Description
Freescale Semiconductor...	MC100ES6221	315Kb / 12P	Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer
Renesas Technology Corp	MC100ES6221	684Kb / 13P	Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer 2019
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Arizona Microtek, Inc	AZ10EL11	76Kb / 6P	ECL/PECL 1:2 Differential Fanout Buffer
Arizona Microtek, Inc	AZ10LVEL11	88Kb / 7P	ECL/PECL 1:2 Differential Fanout Buffer
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Arizona Microtek, Inc	AZ100LVEL11	476Kb / 8P	PECL/ECL 1:2 Differential Fanout Buffer
Renesas Technology Corp	8T33FS6221	1Mb / 23P	Low Voltage 1:20 Differential PECL/HSTL Clock Fanout Buffer Apr 8, 2021
Semtech Corporation	SK100EP111	100Kb / 4P	Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver
Semtech Corporation	SK10EP111	100Kb / 4P	Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver

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