 |
Moteur de recherche de fiches techniques de composants électroniques |
|
|
Moteur de recherche de fiches techniques de composants électroniques |
|
NS32CG16-10 Fiches technique(PDF) 49 Page - National Semiconductor (TI) |
|
|
||||||||||||||||||||||||||||||
NS32CG16-10 Fiches technique(HTML) 49 Page - National Semiconductor (TI) |
|
|
49 / 82 page  30 Functional Description (Continued) 3458 Bus Access Control The NS32CG16 CPU has the capability of relinquishing its control of the bus upon request from a DMA controller or another CPU This capability is implemented by means of the HOLD (Hold Request) and HLDA (Hold Acknowledge) pins By asserting HOLD low an external device requests access to the bus On receipt of HLDA from the CPU the device may perform bus cycles as the CPU at this point has set AD0 – AD15 A16 – A23 and HBE to the TRI-STATE condition and has switched ADS and DDIN to the input mode The CPU now monitors ADS and DDIN from the ex- ternal device to generate the relevant strobe signals (ie TSO DBE RD or WR) To return control of the bus to the CPU the device sets HOLD inactive and the CPU acknowl- edges it by setting HLDA inactive How quickly the CPU releases the bus depends on whether it is idle on the bus at the time the HOLD request is made as the CPU must always complete the current bus cycle Figure 3-25 shows the timing sequence when the CPU is idle In this case the CPU grants the bus during the immedi- ately following clock cycle Figure 3-26 shows the sequence when the CPU is using the bus at the time the HOLD re- quest is made If the request is made during or before the clock cycle shown (two clock cycles before T4) the CPU will release the bus during the clock cycle following T4 If the request occurs closer to T4 the CPU may already have decided to initiate another bus cycle In that case it will not grant the bus until after the next T4 state Note that this situation will also occur if the CPU is idle on the bus but has initiated a bus cycle internally Note 1 During DMA cycles the WAIT1–2 signals should be kept inactive unless they are also monitored by the DMA controller If wait states are required CWAIT should be used Note 2 The logic value of the status pins ST0–3 is undefined during DMA activity TLEE9424 – 75 FIGURE 3-25 HOLD Timing Bus Initially Idle 49 |
Numéro de pièce similaire - NS32CG16-10 |
|
Description similaire - NS32CG16-10 |
|
|
Lien URL |
| Politique de confidentialité |
| ALLDATASHEET.FR |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
French ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
