Low Power CMOS SRAM
128K X 8 Bits
UC62LS1008
-20/-25
Features:
• Vcc operation voltage :
3.0V~ 3.6V
• Low power consumption :
20mA (Max.) operating current
1uA (Typ.) CMOS standby current
• High Speed Access time :
25ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Data retention supply voltage as low as 1.2V
• Easy expansion with CE\ and OE\ options
Description
The UC62LS1008 is a high performance, very low power
CMOS Static Random Access Memory organized as 131,072
words by 8 bits and operates from
3.0V to 3.6V supply
voltage. Advanced CMOS technology and circuit techniques
provide both high speed and low power features with a
typical CMOS standby current of 1uA and maximum access
time of 25ns in 3.0V operation.
Easy memory expansion is provided enable (CE\), and
active LOW output enable (OE\) and three-state output
drivers.
The UC62LS1008 has an automatic power down feature,
reducing the power consumption significantly when chip is
deselected.
The UC62LS1008 is available in the JEDEC standard 32 pin
450mil
Plastic SOP,
8mmx20.0mm
TSOP (type I), and
8mmx13.4mm STSOP.
PRODUCT FAMILY
Power Consumption
Speed
(ns)
STANDBY
Operating
Product Family
Operating
Tempature
Vcc Range
Vcc=3V(Max.)
Vcc=3.3V(Typ.)
Vcc=3.6V(Max.)
Package
Type
UC62LS1008HC
TSOP-32
UC62LS1008FC
SOP-32
UC62LS1008GC
STSOP-32
UC62LS1008AC
0℃ ~ 70℃
3.0V ~ 3.6V
20/25
1uA
20mA
DICE
UC62LS1008HI
TSOP-32
UC62LS1008FI
SOP-32
UC62LS1008GI
STSOP-32
UC62LS1008AI
-40℃ ~ 85℃
3.0V ~ 3.6V
20/25
1uA
20mA
DICE
PIN CONFIGURATIONS
A14
1
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
A2
8
A1
9
A0
10
DQ0
11
DQ1
12
DQ2
13
GND
14
VCC
28
WE
27
A13
26
A8
25
A9
24
A11
23
OE
22
A10
21
CE
20
DQ7
19
DQ6
18
DQ5
17
DQ4
16
DQ3
15
11
12
13
14
16
15
UC62LS1008HC
29
30
31
32
UC62LS1008FI
A15
NC
A16
1
2
3
4
5
6
7
8
9
10
A0
DQ0
DQ1
DQ2
GND
A14
A12
A7
A6
A5
A4
A3
A2
A1
A16
CE2
VCC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
A15
NC
CE2
UC62LS1008GI
17
18
19
20
21
22
23
24
25
26
27
29
28
31
32
30
UC62LS1008FC
UC62LS1008HI
UC62LS1008GC
BLOCK DIAGRAM
MEMORY ARRAY
128K X 8 Bits
COLUMN DECODER
SENSE AMPLIFIER
&
WRITE DRIVER
I/O BUFFER
X8
COL
Address
ROW
Address
CE
WE
OE
CE
WE
OE
CE2
U-Chip Technology Corp. LTD.
Preliminary
Rev. 1.0
Reserves the right to modify document contents without notice.
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