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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AD8316ARM-REEL7 Fiches technique(PDF) 10 Page - Analog Devices |
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AD8316ARM-REEL7 Fiches technique(HTML) 10 Page - Analog Devices |
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10 / 20 page  REV. C –10– AD8316 Further details about the structure and function of log amps are provided in data sheets for other log amps produced by Analog Devices. The AD640 and AD8307 include detailed discussions of the basic principles of operation and explain why the intercept depends on waveform, an important consideration when complex modulation is imposed on an RF carrier. The intercept need not correspond to a physically realizable part of the signal range for the log amp. Thus, for the AD8316, the specified intercept is –62 dBm at 0.9 GHz, whereas the lowest acceptable input for accurate measurement (+1 dB error) is –48 dBm. At 2.5 GHz, the +1 dB error point shifts to –52 dBm. This positioning of the intercept is deliberate and ensures that the VSET voltage is within the capabilities of certain DACs, whose outputs cannot swing below 200 mV. Figure 2 shows the 0.9 GHz response of the AD8316; the vertical axis represents the value required at the power control pin VSET to null the control loop rather than the voltage at the OUT1 or OUT2 pins. PIN 0.5V –67dBm 0 1.5V 1.0V 100 V 80dBV VIN, dBVIN 1mV 60dBV 10mV 40dBV 100mV 20dBV 1V (rms) 0dBV –47dBm –27dBm –7dBm +13dBm –62dBm SLOPE = 22mV/dB IDEAL 0.308V AT –48dBm ACTUAL 1.408V AT +2dBm Figure 2. Basic Calibration of the AD8316 at 0.9 GHz Controller-Mode Log Amps The AD8316 combines the two key functions required for the measurement and control of the power level over a moder- ately wide dynamic range. First, it provides the amplification needed to respond to small signals with a chain of four ampli- fier/limiter cells, each with a small signal gain of 10 dB and a bandwidth of approximately 4 GHz (see Figure 1). At the output of each of these amplifier stages is a full-wave recti- fier, essentially a square-law detector cell that converts the RF signal voltages to a fluctuating current having an average value that increases with signal level. A passive detector stage is added ahead of the first stage. These five detectors are separated by 10 dB, spanning 50 dB of dynamic range. Their outputs are in the form of a differential current, making summation a simple matter. It is readily shown that the summed output can closely approximate a logarithmic function. The overall accu- racy at the extremes of the total range, viewed as the deviation from an ideal logarithmic response, that is, the law-conformance error, can be judged by referring to TPC 4, which shows that errors across the central 40 dB are moderate. Other perfor- mance curves show how conformance to an ideal logarithmic function varies with supply voltage, temperature, and frequency. In a device intended for measurement applications, this current would be converted to an equivalent voltage to provide the log(VIN) function shown in Equation 1. However, the design of the AD8316 differs from standard practice in that its output needs to be a low noise control voltage for an RF power ampli- fier, not a direct measure of the input level. Further, it is highly desirable that this voltage be proportional to the time integral of the error between the actual input VIN and a dc voltage VSET (applied to Pin 3, VSET) that defines the setpoint, that is, a target value for the power level, typically generated by a DAC. This is achieved by converting the difference between the sum of the detector outputs (still in current form) and an internally generated current proportional to VSET to a single-sided current-mode signal. This, in turn, is converted to a voltage (at FLT1 or FLT2, the low-pass filter capacitor nodes) to provide a close approximation to an exact integration of the error between the power present in the termination at the input of the AD8316 and the setpoint voltage. Finally, the voltages developed across the ground referenced filter capacitors CFLT are buffered by a special low noise amplifier of low voltage gain ( ×1.35) and presented at OUT2 or OUT1 for use as the control voltage for the appropriate RF power amplifier. This buffer can provide rail-to-rail swings and can drive a substan- tial load current, including large capacitors. Note: The RF power delivered by the power amplifier is assumed to increase mono- tonically with an increasingly positive voltage on its APC control pin. Band selection in the AD8316 relies on the fact that dual-band/ dual-mode amplifier systems require only one active amplifier at a time. This allows both amplifier outputs to share the RF input of the AD8316 (Pin 1, RFIN) as long as the inactive amplifier is disabled, i.e., it is not delivering RF power. In this case, power control is directed solely through the selected amplifier. The AD8316 ensures that the output control pin associated with the unselected amplifier pulls its APC pin to ground. It is assumed that the amplifier is essentially disabled when its APC pin is grounded. Control Loop Dynamics To understand how the AD8316 behaves in a complete control loop, it is necessary to develop an expression for the current in the integration capacitor as a function of the input VIN and the setpoint voltage VSET. Refer to Figure 3. 1.35 CFLT 4 FLT1 9 VOUT1 VSET VIN IDET SETPOINT INTERFACE 3 RFIN 1 LOGARITHMIC RF DETECTION SUBSYSTEM IERR VSET ISET = VSET / 4.15k IDET = ISLP log10 (VIN/VZ) Figure 3. Behavioral Model for the AD8316 with OUT1 Selected First, write the summed detector currents as a function of the input: II V V DET SLP IN Z = log ( / ) 10 (3) where IDET is the partially filtered demodulated signal, whose exact average value will be extracted through the subsequent integration step; ISLP is the current-mode slope, and has a value of 106 mA per decade (that is, 5.3 mA/dB); VIN is the input in |
Numéro de pièce similaire - AD8316ARM-REEL7 |
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Description similaire - AD8316ARM-REEL7 |
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