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ST8024CDR Fiches technique(PDF) 9 Page - STMicroelectronics |
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ST8024CDR Fiches technique(HTML) 9 Page - STMicroelectronics |
9 / 23 page ST8024 9/23 Table 16: Card Presence Inputs (PINS PRES AND PRES) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) (Note 6) Table 17: Interrupt Output (PIN OFF NMOS Drain With Integrated 20 k Ω PULL-UP Resistor To VDD); (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Table 18: Protection And Limitation (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Table 19: Timing (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Note 1: All parameters remain within limits but are tested only statistically for the temperature range. When a parameter is specified as a function of VDD or VCC it means their actual value at the moment of measurement. Note 2: To meet these specifications, pin VCC should be decoupled to CGND using two ceramic multilayer capacitors of low ESR both with values of 100 nF and 100 nF (see Fig.10). Note 3: Permitted capacitor values are 100 + 100 nF, or 220 nF. Note 4: Transition time and duty factor definitions are shown in Fig.3; δ = t1/(t1+ t2). Note 5: Pin CMDVCC is active LOW; pin RSTIN is active HIGH; for CLKDIV1 and CLKDIV2 functions see Table 20. Note 6: Pin PRES is active LOW; pin PRES is active HIGH see Figs. 8 and 9; PRES has an integrated 1.25 µA current source to GND (PRES to VDD); the card is considered present if at least one of the inputs PRES or PRES is active. Symbol Parameter Test Conditions Min. Typ. Max. Unit VIL Input Voltage LOW -0.3 0.3 VDD V VIH Input Voltage HIGH 0.7 VDD VDD+0.3 V |ILIH| Input Leakage Current HIGH VIH = VDD 5µA |ILIL| Input Leakage Current LOW VIL = 0 5 µA Symbol Parameter Test Conditions Min. Typ. Max. Unit VOL Low Level Output Voltage IOL = 2 mA 0 0.3 V VOH High Level Output Voltage IOH = -15 µA 0.75 VDD V RPU Integrated pull-up resistor 20k Ω Pull-up resistor to VDD 16 20 24 k Ω Symbol Parameter Test Conditions Min. Typ. Max. Unit |ICC(SD)| Shutdown and limitation current pin VCC 90 120 mA II/O(lim) limitation current pins I/O, AUX1 and AUX2 -15 15 mA ICLK(lim) limitation current pin CLK -70 70 mA IRST(lim) limitation current pin RST -20 20 mA TSD Shut down temperature 150 °C Symbol Parameter Test Conditions Min. Typ. Max. Unit tACT Activation time (See Fig. 5) 50 220 µs tDE Deactivation time (See Fig. 7) 50 80 100 µs t3 Start of the window for sending CLK to the card (See Fig. 6) 50 130 µs t5 End of the window for sending CLK to card (See Fig. 6) 140 220 µs tdebounce Debounce time pins PRES and PRES (See Fig. 8) 5 8 11 ms |
Numéro de pièce similaire - ST8024CDR |
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Description similaire - ST8024CDR |
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