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TPS2115APWG4 Fiches technique(PDF) 6 Page - Texas Instruments |
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TPS2115APWG4 Fiches technique(HTML) 6 Page - Texas Instruments |
6 / 20 page TPS2114A TPS2115A SBVS044A − MARCH 2004 − REVISED MAY 2004 www.ti.com 6 TRUTH TABLE D1 D0 VI(IN2) > VI(IN1) STAT OUT(1) 0 0 X Hi-Z IN2 0 1 No 0 IN1 0 1 Yes Hi-Z IN2 1 0 X 0 IN1 1 1 X 0 Hi-Z X = Don’t care. (1)The under-voltage lockout circuit causes the output OUT to go Hi-Z if the selected power supply does not exceed the IN1/IN2 UVLO, or if neither of the supplies exceeds the internal VDD UVLO Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION D0 2 I TTL- and CMOS-compatible input pins. Each pin has a 1- µA pull-up. The truth table shown above illustrates the functionality of D0 and D1. D1 3 I TTL- and CMOS-compatible input pins. Each pin has a 1- µA pull-up. The truth table shown above illustrates the functionality of D0 and D1. GND 5 I Ground IN1 8 I Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above the UVLO threshold and at least one supply exceeds the internal VDD UVLO. IN2 6 I Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is above the UVLO threshold and at least one supply exceeds the internal VDD UVLO. ILIM 4 I A resistor RILIM from ILIM to GND sets the current limit IL to 250/RILIM and 500/RILIM for the TPS2114A and TPS2115A, respectively. OUT 7 O Power switch output STAT 1 O STAT is an open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1 switch is ON or if OUT is Hi-Z (i.e., EN is equal to logic 0). |
Numéro de pièce similaire - TPS2115APWG4 |
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Description similaire - TPS2115APWG4 |
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