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TMP470R1B768PGE Fiches technique(PDF) 1 Page - Texas Instruments |
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TMP470R1B768PGE Fiches technique(HTML) 1 Page - Texas Instruments |
1 / 46 page www.ti.com FEATURES TMS470R1B768 16/32-Bit RISC Flash Microcontroller SPNS108 – AUGUST 2005 • Ten Communication Interfaces: • High-Performance Static CMOS Technology – Five Serial Peripheral Interfaces (SPIs) • TMS470R1x 16/32-Bit RISC Core • 255 Programmable Baud Rates (ARM7TDM™) – Two Serial Communications Interfaces – 60-MHz (Pipeline Mode) (SCIs) – Independent 16/32-Bit Instruction Set • 224 Selectable Baud Rates – Open Architecture With Third-Party Support • Asynchronous/Isosynchronous Modes – Built-In Debug Module – Three High-End CAN Controllers (HECCs) – Utilizes Big-Endian Format • 32-Mailbox Capacity Each • Integrated Memory • Fully Compliant With CAN Protocol, Version 2.0B – 768K-Byte Program Flash • High-End Timer (HET) • 3 Banks With 18 Contiguous Sectors – 32 Programmable I/O Channels: • Internal State Machine for Programming and Erase • 24 High-Resolution Pins – 48K-Byte Static RAM (SRAM) • 8 Standard-Resolution Pins • 15 Dedicated GIO Pins,1 Input-Only GIO Pin, – High-Resolution Share Feature (XOR) and 71 Additional Peripheral I/Os – High-End Timer RAM • Operating Features • 128-Instruction Capacity – Core Supply Voltage (VCC ): 1.81–2.05 V • 16-Channel 10-Bit Multi-Buffered ADC – I/O Supply Voltage (VCCIO): 3.0–3.6 V (MibADC) – Low-Power Modes: STANDBY and HALT – 256-Word FIFO Buffer – Extended Industrial Temperature Range – Single- or Continuous-Conversion Modes • 470+ System Module – 1.55 µs Minimum Sample and Conversion Time – 32-Bit Address Space Decoding – Calibration Mode and Self-Test Features – Bus Supervision for Memory and Peripherals • Eight External Interrupts – Analog Watchdog (AWD) Timer • Flexible Interrupt Handling – Real-Time Interrupt (RTI) • External Clock Prescale (ECP) Module – System Integrity and Failure Detection – Programmable Low-Frequency External Clock (CLK) – Interrupt Expansion Module (IEM) • On-Chip Scan-Base Emulation Logic, IEEE • Direct Memory Access (DMA) Controller Standard 1149.1(1) (JTAG) Test-Access Port – 32 Control Packets and 16 Channels • 144-Pin Plastic Low-Profile Quad Flatpack • Zero-Pin Phase-Locked Loop (ZPLL)-Based (PGE Suffix) Clock Module With Prescaler (1) The test-access port is compatible with the IEEE Standard – Multiply-by-4 or -8 Internal ZPLL Option 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. Boundary scan is not – ZPLL Bypass Mode supported on this device. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ARM7TDM is a trademark of Advanced RISC Machines Limited (ARM). All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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