K5L5628JTM datasheet(3/98 Pages) SAMSUNG

No de pièce	K5L5628JTM

Description	256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

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Fabricant	SAMSUNG [Samsung semiconductor]

Site Internet	http://www.samsung.com/Products/Semiconductor

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Preliminary

K5L5628JT(B)M

Revision 1.0

November 2004

3

MCP MEMORY

Preliminary

The K5L5628JT(B)M is a Multi Chip Package Memory which combines 256Mbit Synchronous Burst Multi Bank NOR Flash Memory

and 128Mbit Synchronous Burst UtRAM.

256Mbit Synchronous Burst Multi Bank NOR Flash Memory is organized as 16M x16 bits and 128Mbit Synchronous Burst UtRAM is

organized as 8M x16 bits.

In 256Mbit Synchronous Burst Multi Bank NOR Flash Memory, the memory architecture of the device is designed to divide its memory

arrays into 519 blocks with independent hardware protection. This block architecture provides highly flexible erase and program capa-

bility. The NOR Flash consists of sixteen banks. This device is capable of reading data from one bank while programming or erasing

in the other bank.

Regarding read access time, the device provides an 14.5ns burst access time and an 88.5ns initial access time at 54MHz. At 66MHz,

the device provides an 11ns burst access time and 70ns initial access time. The device performs a program operation in units of 16

bits (Word) and an erase operation in units of a block. Single or multiple blocks can be erased. The block erase operation is com-

pleted within typically 0.7 sec. The device requires 15mA as program/erase current.

In 128Mbit Synchronous Burst UtRAM, the device is fabricated by SAMSUNG

′s advanced CMOS technology using one transistor

memory cell. The device supports the traditional SRAM like asynchronous bus operation(asynchronous page read and asynchronous

write), and the fully synchronous bus operation(synchronous burst read and synchronous burst write). These two bus operation

modes are defined through the mode register setting. The device also supports the special features for the standby power saving.

Those are the Partial Array Refresh(PAR) mode and internal Temperature Compensated Self Refresh(TCSR) mode.

The optimization of output driver strength is possible through the mode register setting to adjust for the different data loadings.

Through this driver strength optimization, the device can minimize the noise generated on the data bus during read operation.

The K5L5628JT(B)M is suitable for use in data memory of mobile communication system to reduce not only mount area but also

power consumption. This device is available in 115-ball FBGA Type.

GENERAL DESCRIPTION

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