Home Networking PHY with Integrated AFE

LANfinity

™ CN7221

LAN-056, Rev. A

Conexant

5

PROPRIETARY INFORMATION

System Signals

The system level signals provide hardware level

initialization, configuration and status indications from the

device. They are shown in Table 1.

The HLAN_OSC pin is the 60 MHz clock input pin.

The HLAN_IRQ signal is an active-low interrupt signal

intended for use as a level-sensitive interrupt to an external

processor. All interrupt sources are maskable and capable

of being stimulated through software via the ISR and IMR

programmable registers.

Table 1. System Signals

Signal

Description

HLAN_RESET#

Asynchronous system reset

HLAN_IRQ#

Active low processor interrupt

HLAN_OSC

60 MHz oscillator input

Seven Wire Serial (7WS) Interface

Signals

The 7-Wire serial interface provides the digital interface to

the Ethernet MAC.

The seven signals that comprise the 7WS are

HLAN_TX_CLK, HLAN_TX_EN, HLAN_TXD,

HLAN_RX_CLK, HLAN_CRS, HLAN_RXD, and HLAN_COL.

Of these, only HLAN_TX_EN and HLAN_TXD are inputs to

the PHY; the other five are outputs from the PHY. These

signals behave differently depending on which operation is

currently happening in the PHY. The operations of the PHY

are as follows:

•

Idle (no activity in either direction)

•

RxPKT (receiving data)

•

TxPKT (transmitting data).

The subsequent subsections analyze each 7WS-related

state of the PHY in detail.

Table 2. 7WS Interface Signals

Signal

Description

HLAN_TX_CLK

Transmit clock

HLAN_TX_EN

Transmit enable

HLAN_TXD

Transmit data

HLAN_RX_CLK

Receive clock

HLAN_CRS

Receive carrier sense

HLAN_RXD

Receive data

HLAN_COL

Collision (active high)

Idle State

HLAN_TX_CLK

HLAN_TX_EN

HLAN_TXD

HLAN_RX_CLK

HLAN_CRS

HLAN_RXD

HLAN_COL

HLAN_RX_CLK and HLAN_TX_CLK are synchronized to the same phase. All other signals are inactive. The two clock signals

toggle low for 116.7ns and high for 466.7ns, for an overall period of 583.3ns (about 1.7MHz).