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TPS2340APFPRG4 Fiches technique(PDF) 7 Page - Texas Instruments

No de pièce TPS2340APFPRG4
Description  DUAL-SLOT PCI HOT-PLUG POWER CONTROLLER
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

TPS2340APFPRG4 Fiches technique(HTML) 7 Page - Texas Instruments

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TPS2340A
SLUS528A – MARCH 2002 – REVISED AUGUST 2002
7
www.ti.com
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
3VAUXI
66
I
3.3Vaux voltage supply input. A 0.1-
µF bypass capacitor to PWRGND is recommended.
3VAUXA
65
O
3 3Vaux voltage supply outputs A 0 01 F bypass capacitor to PWRGND is recommended
3VAUXB
64
O
3.3Vaux voltage supply outputs. A 0.01-
µF bypass capacitor to PWRGND is recommended.
3VISA
57
I
Connect to the load side of the sense resistor. See definition for 3VS. This pin has a switched FET to
ground to discharge any output load capacitance when the output is turned off A 0 01
µF bypass ca
3VISB
4
I
ground to discharge any output load capacitance when the output is turned off. A 0.01-
µF bypass ca-
pacitor to ANAGND is recommended.
3VSA
58
I
Connect to the source side of the 3.3-V FET switch. This pin in conjunction with the 3VIS pin sense
the current to the 3 3 V load by sensing the voltage drop across a sense resistor A 0 01
µFbypass
3VSB
3
I
the current to the 3.3-V load by sensing the voltage drop across a sense resistor. A 0.01-
µF bypass
capacitor to ANAGND is recommended.
5V3VGA
59
O
Gate drive for the 5-V and 3.3-V FET switches. Ramp rate is programmed by external capacitance
connected from this pin to PWRGND. The capacitor is charged with a 20-
µA current source and dis-
5V3VGB
2
O
connected from this in to PWRGND. The ca acitor is charged with a 20-
µA current source and dis-
charged with a switch. The output UV circuitry is disabled until the voltage on this pin is greater than
11 V and the voltage on P12VGx is greater than 20 V.
5VISA
56
I
Connect to the load side of the sense resistor. See definition for 5VS. 5VIS is also used to sense the
output voltage for the 5-V UV circuit. This pin has a switched FET to ground to discharge any output
5VISB
5
I
out ut voltage for the 5-V UV circuit. This in has a switched FET to ground to discharge any out ut
load capacitance when the output is turned off. A 0.01-
µF bypass capacitor to ANAGND is recom-
mended.
5VSA
55
I
Connect to the source of the 5-V FET switch. This pin in conjunction with the 5VIS pin senses the
current to the 5V load by sensing the voltage drop across the sense resistor A 0 01
µFbypass capaci
5VSB
6
I
current to the 5V load by sensing the voltage drop across the sense resistor. A 0.01-
µF bypass capaci-
tor to ANAGND is recommended.
ANAGND
54
Ground pin for the low level analog section
ATTLEDA
47
O
ATTLEDx is a high current low true open drain output with a 100 k
Ω pull up resistor to V5IN
ATTLEDB
13
O
ATTLEDx is a high-current, low-true, open-drain output with a 100-k
Ω pull-up resistor to V5IN.
BUSENA
32
O
Output to bus enable FET switches These outputs typically enable PCI clocks to the PCI connector
BUSENB
29
O
Output-to-bus enable FET switches. These outputs typically enable PCI clocks to the PCI connector.
BUTTONA
45
I
PCI hot-plut attention notification (momentary) button inputs. Low indicates attention. These input have
hysteresis and a 100 k
Ω pull up to DIGVCC requiring only a capacitor to ground for debouncing me
BUTTONB
15
I
hysteresis and a 100-k
Ω pull-up to DIGVCC, requiring only a capacitor to ground for debouncing me-
chanical noise.
CLKENA
33
O
O tp t to clock enable FET s itches These o tp ts t picall enable PCI clocks to the PCI connector
CLKENB
28
O
Output-to-clock enable FET switches. These outputs typically enable PCI clocks to the PCI connector.
DIGVCC
30
I
Power pin for the digital section, connect to 3.3 V. A 0.1-
µF bypass capacitor from DIGVCC to
DIGGND is recommended.
DIGGND1
31
DIGGND2
18
Ground pins for the digital section.
DIGGND3
43
Ground ins for the digital section.
M12VGA
69
O
A capacitor connected from this pin to M12VO programs the ramp rate of the 12-V switched output.
M12VGB
78
O
A ca acitor connected from this in to M12VO rograms the ram rate of the 12-V switched out ut.
The capacitor is charged with a 20-
µA current source and discharged with a switch.
M12VINA
68
I
–12-V input voltage to the device and the –12-V power FET. M12VINA and M12VINB must be tied
together and are internally connected by a high resistance path The tab on the back of the package is
M12VINB
79
I
together and are internally connected by a high-resistance path. The tab on the back of the package is
also connected to M12VIN. A 0.1-
µF bypass capacitor from M12VIN to PWRGND is recommended.
M12VOA
67
O
–12-V Switched output. This pin has a switched FET to ground to discharge any output load capaci-
M12VOB
80
O
–12-V Switched out ut. This in has a switched FET to ground to discharge any out ut load ca aci-
tance when the output is turned off. A 0.01-
µF bypass capacitor to PWRGND is recommended.
M66ENA
34
I
PCI 66MHz–capable bit for slot A. This pin has a 100-k
Ω pull-up to 3VISA. This pin is typically tied to
the PCI connector.
M66ENB
27
I
PCI 66MHz–capable bit for slot B. This pin has a 100-k
Ω pull-up to 3VISB. This pin is typically tied to
the PCI connector.
OCSET
7
I
A resistor connected between this pin and ANAGND sets the overcurrent threshold of the 4 FET
switches. The +12-V and –12-V switches are set for the maximum permissible currents per the PCI
specification when a 1%, 6.04-k
Ω resistor is used. A 0.1-µF bypass capacitor from OCSET to
ANAGND is recommended.


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