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TPS2340APFP Fiches technique(PDF) 8 Page - Texas Instruments |
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TPS2340APFP Fiches technique(HTML) 8 Page - Texas Instruments |
8 / 27 page TPS2340A SLUS528A – MARCH 2002 – REVISED AUGUST 2002 8 www.ti.com Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION P12VGA 70 O Gate drive for the 12-V internal N-channel MOSFET for slot A. Connect a capacitor from this pin to PWRGND to program the ramp rate. The capacitor is charged with a 5– µΑ current source and dis- charged with a switch. The output undervoltage circuitry is disabled until the voltage on this pin is greater than 20 V and the voltage on 5V3VGA is greater than 11 V. P12VGB 77 O Gate drive for the 12-V internal N-channel MOSFET for slot B. Connect a capacitor from this pin to PWRGND to program the ramp rate. The capacitor is charged with a 5- µΑ current source and dis- charged with a switch. The output undervoltage circuitry is disabled until the voltage on this pin is greater than 20 V and the voltage on 5V3VGB is greater than 11 V. P12VINA 72 I 12-V input to the device and the 12-V power FET for slot A. A 0.1- µF bypass capacitor from P12VINA P12VINA 73 I 12-V in ut to the device and the 12-V ower FET for slot A. A 0.1- µF by ass ca acitor from P12VINA to PWRGND is recommended. P12VINB 75 I 12-V input to the device and the 12-V power FET for slot B. A 0.1- µF bypass capacitor from P12VINB P12VINB 74 I 12-V in ut to the device and the 12-V ower FET for slot B. A 0.1- µF by ass ca acitor from P12VINB to PWRGND is recommended. P12VOA 71 O 12-V switched output for slot A. This pin has a switched FET to ground to discharge any output load capacitance when the output is turned off. A 0.01- µF bypass capacitor to PWRGND is recommended. P12VOB 76 O 12-V switched output fo rslot B. This pin has a switched FET to ground to discharge any output load capacitance when the output is turned off. A 0.01- µF bypass capacitor to PWRGND is recommended. PCIXCAPA 50 I PCI–X capable bit. To select 133-MHz PCI–X mode, leave PCIXCAPx floating. For 66-MHz PCI–X mode, pull down PCIXCAPx with one or two 10-k Ω resistors. For 33-MHz PCI 2.2 mode, ground PCIXCAPB 11 I mode, ull down PCIXCAPx with one or two 10-k Ω resistors. For 33-MHz PCI 2.2 mode, ground PCIXCAPx. This pin has a 10-k Ω pull–up resistor to DIGVCC. This pin is typically tied to the PCI con- nector. PGOOD 38 I Power good input. PGOOD has hysteresis so that it can be used as a power-on reset, driven from a slow-rising RC. PGOOD also has a 100-k Ω pull-up to DIGVCC. A logic path in the TPS2340A pre- vents the input data state machine from being reset when SOR asserts. This can be corrected with an external AND gate, which causes PGOOD to be de-asserted whenever SOR is asserted. (See Note 1.) PMEA 62 I PME input from slot A. These signals comply with PCI Power Management Spec 1.1. PMEA has a 200-k Ω pull-up to the appropriate switched 3VAUX for precharging. This pin is typically tied to the PCI connector. PMEB 63 I PME input from slot B. These signals comply with PCI Power Management Spec 1.1. PMEB has a 200-k Ω pull-up to the appropriate switched 3VAUX for precharging. This pin is typically tied to the PCI connector. PMEO 61 O PME output from the device. This signal is an open-drain output and complies with PCI Power Man- agement Specification 1.1 PME definition. PRSNT1A 37 I PCI presence detect bit 1. This input has hysteresis and a 100-k Ω pull-up to DIGVCC, requiring only a PRSNT1B 24 I PCI resence detect bit 1. This in ut has hysteresis and a 100-k Ω ull-u to DIGVCC, requiring only a capacitor to ground for debouncing mechanical noise. This pin is typically tied to the PCI connector. PRSNT2A 36 I PCI–presence detect bit 2. This input has hysteresis and a 100-k Ω pull–up to DIGVCC, requiring only PRSNT2B 25 I PCI– resence detect bit 2. This in ut has hysteresis and a 100-k Ω ull–u to DIGVCC, requiring only a capacitor to ground for debouncing mechanical noise. This pin is typically tied to the PCI connector. PWRGND1 1 _ Gro nd pin for the po er analog section PWRGND2 60 – Ground pin for the power analog section. PWRLEDA 48 O In normal operation, output-to-power indicator PCI hot-plug status LED. In test mode, indicates the state of the internal signal PWRENx the power FET control signal PWRLEDx is a high current low PWRLEDB 12 O state of the internal signal PWRENx, the power FET control signal. PWRLEDx is a high-current, low- true open-drain output with a 100-k Ω pull-up resistor. NOTE 1: PGOOD input: diagram: UDG–01126 38 40 TPS2340 PGOOD PWRGOOD (FROM PLATFORM) SOR (FROM HPC) SOR |
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