No. 5877-10/14

LC72720N, 72720NM

Note: The output indicates the synchronization state for the previous block.

Mode (PT2 = 0)

The SYNC pin

0 to 2

When synchronized: Low (0). When unsynchronized: High (1)

When synchronized: Goes high for a fixed period (421 µs) at

3

the start of a block and then goes low.

When unsynchronized: High (1)

When PT2 = 0

The RDS-ID pin

No RDS

High (1)

RDS present

Low (0)

10. Test mode settings (4 bits): TS0 to TS3

Initial values: TS0 = 0, TS1 = 0, TS2 = 0, TS3 = 0

(Applications must set these bits to the above values.)

Note: T1 and T2 pins (pins 7 and 8) are related to test mode as follows:

Initial values: CT0 = 0, CT1 = 0

Pin T1

Pin T2

IC operation

Notes

0

0

Normal operating mode

These states are user settable

0

1

Standby mode (crystal oscillator stopped)

1

0/1

IC test mode

Users cannot use this state

11. Circuit control (2 bits): CT0 and CT1

RDCL/RDDA/RSFT and ERROR/CORREC/SYNC Output Timing

Timing 1 (modes 1 to 3, PT2 = 0)

Timing 2 (mode 3, PT2 = 0)

Item

Control

CT0

RSFT control

When set to 1, soft-decision control data (RSFT) is easier to generate.

CT1

RDS-ID detection condition

When set to 1, the RDS-ID detection conditions are made more restrictive.

RDCL output

RDDA output

RSFT output

Input data

Error crrection

SYNC output

ERROR output

CORREC output

Sync NG

Sync NG

Sync NG

Sync OK

Sync OK

Sync OK

Sync OK

Sync OK

Data

corrected

Data

corrected

No

errors

No

errors

Note: When PT2 = 0, RDDA and RSFT must be

aquired on the falling edge of RDCL.