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MT90866 Fiches technique(PDF) 2 Page - Zarlink Semiconductor Inc |
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MT90866 Fiches technique(HTML) 2 Page - Zarlink Semiconductor Inc |
2 / 86 page MT90866 Data Sheet 2 Zarlink Semiconductor Inc. The MT90866 also offers a sub-rate switching configuration which allows 2-bit wide 16kb/s or 4-bit wide 32 kb/s data channels to be switched within the device. The device has features that are programmable on a per-stream or a per-channel basis including message mode, input delay offset, output advancement offset, direction control, and high impedance output control. The MT90866 supports all three of the H.110 specification required clocking modes: Primary Master, Secondary Master and Slave. Figure 1 - Functional Block Diagram STi0 STi27 Test Port Output Mux Backplane Data Memory VSS VDD RESET Interface Backplane Converter P/S & S/P C20i STo0 STo27 LCSTo (4,096 channels) Local Connection Memory ODE P/S Converter Local Interface S/P Converter Local Interface STio0 STio31 (2,432 locations) Local Data Memory (2,432 channels) Backplane Connection Memory (4,096 locations) Internal Registers & Microprocessor Interface Output Mux APLL DPLL BCSTo HiZ Control HiZ Control Local Interface Timing Unit ST_FPo0 ST_CKo0 VDD5V ST_FPo1 ST_CKo1 PCI_OE TM1 TM2 SG1 AT1 DT1 |
Numéro de pièce similaire - MT90866 |
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Description similaire - MT90866 |
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