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SI5540-BC Fiches technique(PDF) 11 Page - Silicon Laboratories |
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SI5540-BC Fiches technique(HTML) 11 Page - Silicon Laboratories |
11 / 20 page S i5540 Preliminary Rev. 0.31 11 Differential Output Circuitry The Si5540 utilizes a current-mode logic (CML) architecture to drive the high speed serial output clock and data on TXCLKOUT and TXDOUT. An example of output termination with ac coupling is shown in Figure 4. In applications where direct dc coupling is possible, the 250 nF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2 on page 5. Figure 4. CML Output Driver Termination (TXCLKOUT, TXDOUT) 1.5 V 50 Ω 50 Ω 24 mA Zo = 50 Ω Zo = 50 Ω 50 Ω 50 Ω VDD VDD 250 nF 250 nF |
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Description similaire - SI5540-BC |
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