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SN74LS192D Fiches technique(PDF) 1 Page - ON Semiconductor

No de pièce SN74LS192D
Description  PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

SN74LS192D Fiches technique(HTML) 1 Page - ON Semiconductor

  SN74LS192D Datasheet HTML 1Page - ON Semiconductor SN74LS192D Datasheet HTML 2Page - ON Semiconductor SN74LS192D Datasheet HTML 3Page - ON Semiconductor SN74LS192D Datasheet HTML 4Page - ON Semiconductor SN74LS192D Datasheet HTML 5Page - ON Semiconductor SN74LS192D Datasheet HTML 6Page - ON Semiconductor SN74LS192D Datasheet HTML 7Page - ON Semiconductor  
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5-1
FAST AND LS TTL DATA
PRESETTABLE BCD/DECADE
UP/DOWN COUNTER
PRESETTABLE 4-BIT BINARY
UP/DOWN COUNTER
The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the
SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate
Count Up and Count Down Clocks are used and in either counting mode the
circuits operate synchronously. The outputs change state synchronous with
the LOW-to-HIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count Down outputs are
provided which are used as the clocks for a subsequent stages without extra
logic, thus simplifying multistage counter designs. Individual preset inputs
allow the circuits to be used as programmable counters. Both the Parallel
Load (PL) and the Master Reset (MR) inputs asynchronously override the
clocks.
Low Power . . . 95 mW Typical Dissipation
High Speed . . . 40 MHz Typical Count Frequency
Synchronous Counting
Asynchronous Master Reset and Parallel Load
Individual Preset Inputs
Cascading Circuitry Internally Provided
Input Clamp Diodes Limit High Speed Termination Effects
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
CONNECTION DIAGRAM DIP (TOP VIEW)
14
13
12
11
10
9
1
2345
6
7
16
15
8
VCC
P1
P0
MR
TCD TCU
P2
PL
P3
Q1
Q0
CPD CPU
Q2
Q3
GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
CPU
CPD
MR
PL
Pn
Qn
TCD
TCU
Count Up Clock Pulse Input
Count Down Clock Pulse Input
Asynchronous Master Reset (Clear) Input
Asynchronous Parallel Load (Active LOW) Input
Parallel Data Inputs
Flip-Flop Outputs (Note b)
Terminal Count Down (Borrow) Output (Note b)
Terminal Count Up (Carry) Output (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40
µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
SN54/74LS192
SN54/74LS193
PRESETTABLE BCD / DECADE
UP / DOWN COUNTER
PRESETTABLE 4-BIT BINARY
UP / DOWN COUNTER
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN
Plastic
SN74LSXXXD
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
VCC = PIN 16
GND = PIN 8
5
4
32
6
7
12
9
10
1
15
11
CPD
Q0 Q1 Q2 Q3
TCD
P3
P2
P1
P0
PL
CPU
TCU
13
MR
14


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