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TSB42AA9PZT Fiches technique(PDF) 11 Page - Texas Instruments |
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TSB42AA9PZT Fiches technique(HTML) 11 Page - Texas Instruments |
11 / 45 page 2–1 2 Detailed Description TASB42AA9 comprises: • IEEE P1394a Compliant Link Core • Receive Packet Router • Transmit Packetizer • SBP–2 Transport Protocol Engine • FIFOs (Control Tx/Rx and Data) • Embedded 8052 Processor • Internal ROM (16K × 8) • Configuration ROM Registers (Parameter RAM) • ATA/ATAPI Interface • Flash PROM/EPROM Interface • 2-wire Serial EEPROM Bus Interface 2.1 Functional Block Diagram The functional block architecture of TSB42AA9 is shown in Figure 2–1. SBP-2 Engine Data FIFO Fetch Agent and Status Send Data Transfer Control Command Agent Management Agent ATA/ATAPI I/F Tx/Rx Control FIFO (256 Byte) 8052 Embedded Processor Flash PROM/ EPROM I/F Serial EEPROM Bus I/F 16 k × 8 Internal ROM Receive Packet Router Packetizer Parameter RAM CSR and Configuration ROM Access 1394a Link Core Figure 2–1. StorageLynx Block Diagram 2.2 Functional Block Descriptions 2.2.1 IEEE 1394a Link Core The TSB42AA9 contains an IEEE P1394a compatible link core. The link layer is the protocol layer responsible for the interface between the transaction layer and physical layers for asynchronous transactions. The link core |
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