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TSB42AA9PZT Fiches technique(PDF) 10 Page - Texas Instruments

No de pièce TSB42AA9PZT
Description  STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

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TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
PHY INTERFACE
CTL1, CTL0
15, 16
I/O
PHY-link control bus. CTL1 and CTL0 indicate the four operations that can occur on this interface (see
Annex J of the IEEE 1394-1995 standard[2] for more information about the four operations).
D7 – D0
6, 7, 8, 9, 11,
12, 13, 14
I/O
PHY-link data bus. Data is expected on D0–1 for 100 Mb/s packets, D0–D3 for 200 Mb/s, and D0–D7 for
400 Mb/s. D0 is the most significant bit.
LREQ
18
O
Link request. LREQ is an output that makes bus requests and register access requests to the PHY.
SCLK
17
I
System clock. SCLK is a 49.152-MHz clock supplied by the PHY
±100 ppm.
FLASH PROM/EPROM INTERFACE
ADDR[13:0]
87, 83, 91, 93,
89, 88, 82, 79,
78, 77, 75, 74,
73, 72
O
Flash PROM/EPROM address bus. ADDR is a 14-bit address bus between StorageLynx and its
(optional) external memory. ADDR13 is the most significant bit.
AD[7:0]
4, 3, 1, 100,
99, 98, 97, 96
I/O
Flash PROM/EPROM data bus. AD is a birdirectional 8-bit data bus between StorageLynx and its (op-
tional) external memory. AD7 is the most significant bit.
CS
95
O
Flash PROM/EPROM chip enable (active low). CS is the external memory chip enable.
OE_RD
92
O
Flash PROM/EPROM output enable (active low). OE_RD is the external memory output enable.
WE
85
O
Flash PROM/EPROM write enable (active low). WE is the external memory write enable. During normal
operation this signal is asserted high.
2-wire Serial Bus
SDA
23
I/O
Serial Data. SDA is the data interface for the serial EEPROM. SDA should be pulled up with a 10K resis-
tor at the serial EEPROM.
SCL
24
O
Serial Clock. SCL provides serial clock signaling. 100 kHz (Nclk/256) for serial EEPROM.
RESERVED
RSVD
25, 26, 27
Reserved. Test Signals
MISCELLANEOUS
UART_RXD
28
I
UART RXD. Mux-selectable input. On power up, this signal is sampled to set the embedded processor
clock speed setting. A detected logic high sets the internal clock to 50 MHz (pull-up through a 10K resis-
tor). A logic low sets the clock to 25 MHz (pull down through a 1K resistor).
UART_TXD
30
O
UART TXD. Mux-selectable output.
MODE0
69
I
MODE0. This signal is device configuration select 0. See Table 2–4.
MODE1
70
I
MODE1. This signal is device configuration select 1. See Table 2–4.
PWRON
34
O
Power on. This signal is asserted on power up. PWRON is negated when an SBP–2 logout occurs. This
signal can also be used as a general-purpose output.
TSTMODE
19
I
Test mode select. Tie to GND during normal operation.
SCANEN
20
I
Test mode scan enable. Tie to GND during normal operation.
1.6
Chapter References
1.
IEEE P1394a, Draft Standard for a High Performance Serial Bus (Supplement)
2.
IEEE Std 1394–1995, Standard for a High Performance Serial Bus
3.
T10 Project 1155D, ANSI NCTIS.xxx-199x, Serial Bus Protocol 2 (SBP-2)


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