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KM23V8105G Fiches technique(PDF) 3 Page - Samsung semiconductor |
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KM23V8105G Fiches technique(HTML) 3 Page - Samsung semiconductor |
3 / 5 page KM23V8105D(G) CMOS MASK ROM TEST CONDITIONS Item Value Input Pulse Levels 0.45V to 2.4V Input Rise and Fall Times 10ns Input and Output timing Levels 1.5V Output Loads 1 TTL Gate and CL=100pF AC CHARACTERISTICS (TA=0 °C to +70°C, VCC=3.3V/3.0V±0.3V, unless otherwise noted.) READ CYCLE NOTE : Page Address is determined as below. Word mode (BHE = VIH) : A0, A1 Byte mode (BHE = VIL) : A-1, A0, A1 Item Symbol Vcc=3.3V ±0.3V Vcc=3.0V ±0.3V Unit Min Max Min Max Read Cycle Time tRC 100 120 ns Chip Enable Access Time tACE 100 120 ns Address Access Time tAA 100 120 ns Page Address Access Time tPA 30 50 ns Output Enable Access Time tOE 30 50 ns Output or Chip Disable to Output High-Z tDF 20 20 ns Output Hold from Address Change tOH 0 0 ns |
Numéro de pièce similaire - KM23V8105G |
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Description similaire - KM23V8105G |
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