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AD10226 Fiches technique(PDF) 11 Page - Analog Devices |
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AD10226 Fiches technique(HTML) 11 Page - Analog Devices |
11 / 20 page REV. 0 AD10226 –11– Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the worst harmonic component. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. Minimum Conversion Rate The ENCODE rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The ENCODE rate at which parametric testing is performed. Output Propagation Delay The delay between the 50% point of the rising edge of ENCODE command and the time when all output data bits are within valid logic levels. Power Supply Rejection Ratio The ratio of a change in output offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full-scale) to the rms value of the sum of all other spectral components, excluding the first six harmonics and dc. [May be reported in dBc (i.e., degrades as signal levels are lowered) or in dBFS (always related back to converter full-scale).] Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full-scale) to the rms value of the sum of all other spectral components, excluding the first six harmonics and dc. [May be reported in dBc (i.e., degrades as signal levels are lowered) or in dBFS (always related back to converter full-scale).] Spurious-Free Dynamic Range The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. [May be reported in dBc (i.e., degrades as signal levels is lowered) or in dBFS (always related back to converter full-scale).] Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc. Voltage Standing Wave Ratio (VSWR) The ratio of the amplitude of the electric field at a voltage maximum to that at an adjacent voltage minimum. APPLICATION NOTES Theory of Operation The AD10226 is a high-dynamic-range dual 12-bit, 125 MHz subrange pipeline converter that uses switched capacitor archi- tecture. The analog input section uses AINA2/B2 at 1.84 V p-p with an input impedance of 50 Ω. The analog input includes an ac-coupled wideband 1:1 transformer, which provides high dynamic range and SNR while maintaining VSWR and gain flatness. The ADC includes a high bandwidth linear track/hold that gives excel- lent spurious performance up to and beyond the Nyquist rate. The high bandwidth track/hold has a low jitter of 0.25 ps rms, leading to excellent SNR and SFDR performance. AC-coupled differen- tial PECL/ECL encode inputs are recommended for optimum performance. USING THE AD10226 ENCODE Input Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track/hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock will be combined with the desired signal at the A/D output. For that reason, considerable care has been taken in the design of the ENCODE input of the AD10226, and the user is advised to give commensurate thought to the clock source. The monolithic converter has an internal clock duty cycle stabiliza- tion circuit that locks to the rising edge of ENCODE (falling edge of ENCODE if driven differentially), and optimizes timing inter- nally. This allows for a wide range of input duty cycles at the input without degrading performance. Jitter in the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. This circuit is always on and cannot be dis- abled by the user. The ENCODE and ENCODE inputs are internally biased to 3.75 V (nominal) and support either differential or single-ended signals. For best dynamic performance, a differential signal is recommended. Good performance is obtained using an MC10EL16 in the circuit to directly drive the encode inputs, as illustrated in Figure 2. GND 510 510 0.1 F 0.1 F PECL GATE ENCODE ENCODE AD10226 Figure 2. Using PECL to Drive ENCODE Inputs Often, the cleanest clock source is a crystal oscillator producing a pure, single-ended sine wave. In this configuration, or with any roughly symmetrical, single-ended clock source, the signal can be ac-coupled to the ENCODE input. To minimize jitter, the signal amplitude should be maximized within the input range described in the Table II. Table II. ENCODE Inputs Description Min Nom Max Differential Signal Amplitude (VID) 200 mV 750 mV 5.5 V Input Voltage Range (VHID, VILD, VHIS) –5 V VCC + 0.5 V Internal Common-Mode Voltage (VICM)3.75 V External Common-Mode Bias (VECM) 2.0 V 4.25 V 50 50 50 0.1 F AD10226 ENCODE ENCODE 50 SINE SOURCE 0.1 F Figure 3. Single-Ended 50 Sine Encode Circuit The 10 k Ω resistors to ground at each of the inputs, in parallel with the internal bias resistors, set the common-mode voltage to ~ 2.5 V, |
Numéro de pièce similaire - AD10226 |
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Description similaire - AD10226 |
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