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CH5001A Datasheet(Fiches technique) 6 Page - List of Unclassifed Manufacturers

Numéro de pièce CH5001A
Description  CMOS COLOR DIGITAL VIDEO CAMERA
Télécharger  34 Pages
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Fabricant  ETC1 [List of Unclassifed Manufacturers]
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6
201-0000-032 Rev 3.0, 6/2/99
CHRONTEL
CH5001A
Functional Description
The CH5001 accepts a light input to a photosensitive array, and produces a digital video stream in response.
Each photodiode in the array is covered with a red, green or blue filter whose spectral response is designed to
provide a proper color picture when displayed on a standard monitor/TV. The internal functions performed are:
Scanning of the photodiode array into a serial data stream.
Programmable gain sample and hold with programmable offset.
Digitization of data stream.
Transform the data from the color filter domain to RGB domain.
Programmable gamma correction and RGB offset.
Conversion from RGB to YCrCb domain.
Interpolate/Decimate data to desired resolution
Formatting of the data stream for the desired type of output.
Automatic Shutter, Gain and Black Setting.
Timing signal generation.
Bus control.
Power up control of key register bits
Scanning of the photodiode array:
The CH5001 serializes the data captured in the photo array, and outputs one pixel of data each clock period.
The first row is output a programmable number of lines after the leading edge of the vertical sync output. After
the entire row has been output, the next row will be addressed and output. Correlated double sampling tech-
niques are used during readout to reduce fixed pattern noise. After this transfer is complete, pixel data is seri-
ally sent to the programmable gain amplifier and then to an A/D converter.
Programmable gain sample and hold:
The programmable gain is divided into two sections. The first gain block is controlled by PGSH[2:0] and the
second by the ADFS control. ADFS can be treated as the MSB of the gain control, and a plot of gain versus
control setting is shown below. The programmable gain section also provides a bias adjustment, under the con-
trol of the an chip DAC. When the ASBE bit is a one (default) this DAC value is determined automatically, via
a feedback loop which monitors the A/D output signal. When the ASBE bit is a zero, the DAC can be con-
trolled via BCLMP[7:0].
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GaindB
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Gain
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