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CH5001A Fiches technique(PDF) 16 Page - List of Unclassifed Manufacturers

No de pièce CH5001A
Description  CMOS COLOR DIGITAL VIDEO CAMERA
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Fabricant  ETC1 [List of Unclassifed Manufacturers]
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CH5001A Fiches technique(HTML) 16 Page - List of Unclassifed Manufacturers

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201-0000-032 Rev 3.0, 6/2/99
CHRONTEL
CH5001A
Register
Symbol
Address
(Hex)
Default
Value
Description
Cr Gain
CRG
15
1011
1010
Gain applied to the Cr color difference signal.
Cb Gain
CBG
16
1001
0011
Gain applied to the Cb color difference signal.
PSH Gain
Gamma
PSHG
17
0001
1001
0-2: Selects the gain of the programmable
sample and hold.
4,5: Selects Gamma correction value
Clamp Level
BCLMP
18
1000
0000
Selects the level that the black level clamp
adjusts to during dark pixel.
Miscellaneous
MISC
19
1000
1000
7,6,5: Reserved
4: Power Down
3: V Sync. Polarity
2: H Sync. Polarity
1,0: Border Color
Device ID
DID
1A
0010
0000
The four MSBs hold the device ID. The four
LSBs hold the version ID.
Test Register
TST
1B
0000
0000
Test Register
Test Memory
TM
1C
0000
0000
Test Register
Auto-Shutter Enable
ASE
1D
1110
0100
Enables and controls the following autoshutter
algorithm parameters:
7: Enables the AS to control the shutter
6: Enables the AS to control black level
5: Enables the AS to control programmable
gain.
4,3: Reserved
2-0: Determines the threshold of the shutter
gain setting to enable black level changes.
Auto-Shutter Window and
Input Control Bits
ASW
1E
x100
PUD[3:0]
Used to select the autoshutter window, display
window, and select input data to algorithm:
6: Autoshutter max input enable
5: Autoshutter A/D or CSC select
4: Window Display
3-0: Window Select
Auto-Shutter Black Count
Threshold Value
ASBC
1F
1111
1001
Determines the threshold that compares the
Black Sense value.
Auto-Shutter White Count
Threshold Value
ASWC
20
1000
0000
Determines the threshold that compares the
White Sense value.
Extended Shutter Bits
ESLE
21
xxx0
0000
ESLE (MSB) along with ESLH and ESLL form
the overall Shutter Length Control Register.
Miscellaneous 2
MISC2
22
0001
1001
Determines Master clock frequency, CLKOUT
control, and A/D Direct Output mode
Miscellaneous 3
MISC3
23
0011
1001
Determines internal clock delay and A/D full
scale value
Power Down Register
PD
24
xxx1
0000
4: ResetB provides software reset
3-0: Reserved.
Address Register
AR
26
0000
0000
Holds the address of the IIC register being
accessed
Table 5. Register Descriptions


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