7-851

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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CD4035BMS

CMOS 4 -Stage Parallel

In/Parallel Out Shift Register

Description

CD4035BMS is a four stage clocked signal serial register

with provision for synchronous PARALLEL inputs to each

stage and SERIAL inputs to the first stage via JK logic. Reg-

ister stages 2, 3, and 4 are coupled in a serial D flip-flop con-

figuration

when

the

register

is

in

the

serial

mode

(PARALLEL/SERIAL control low).

Parallel entry into each register stage is permitted when the

PARALLEL/SERIAL control is high.

In the parallel or serial mode information is transferred on

positive clock transitions.

When the TRUE/COMPLEMENT control is high, the true

contents of the register are available at the output terminals.

When the TRUE/COMPLEMENT control is low, the outputs

are the complements of the data in the register. The TRUE/

COMPLEMENT

control

functions

asynchronously

with

respect to the CLOCK signal.

JK input logic is provided on the first stage SERIAL input to

minimize logic requirements particularly in counting and

sequence-generation applications. With JK inputs connected

together, the first stage becomes a D flip-flop. An asynchro-

nous common, RESET is also provided.

The CD4035BMS series type is supplied in these 16 lead

outline packages

Braze Seal DIP

H4T

Frit Seal DIP

H1F

Ceramic Flatpack

H6W

Features

•J - K Serial Inputs and True/Complement Outputs

• High Voltage Type (20V Rating)

• 4-Stage Clocked Shift Operation

• Synchronous Parallel Entry on All 4 Stages

•JK Inputs on First Stage

• Asynchronous True/Complement Control on All Out-

puts

• Static Flip-Flop Operation; Master-Slave Configura-

tion

• Buffered Inputs and Outputs

• High Speed Operation 12MHz (Typ) at VDD = 10V

• 100% Tested for Quiescent Current at 20V

• Standardized, Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Meets All Requirements of JEDEC Tentative Standard

Number 13A, “Standard Specifications for Description

of ‘B’ Series CMOS Devices”

Applications

• Counters, Registers

- Arithmetic-Unit Registers

- Shift Left/Shift Right Registers

- Serial-to-Parallel/Parallel-to-Serial Conversions

• Sequence Generation

• Control Circuits

• Code Conversion

December 1992

File Number

3308

Pinout

CD4035BMS

TOP VIEW

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

Q1/Q1

TRUE/

K

J

RESET

CLOCK

VSS

P/S

VDD

Q3/Q3

Q4/Q4

PI-4

PI-3

PI-2

PI-1

Q2/Q2

COMP.

Functional Diagram

PARALLEL IN

4

3

6

7

2

5

J

K

CLK

P/S

T/C

RESET

VDD = 16

VSS = 8

9

1

10

2

11

3

12

4

1

151413

Q1/Q1 Q2/Q2 Q3/Q3 Q4/Q4

T/C OUT

4-STAGE REGISTER

SER

IN

FIRST STAGE TRUTH TABLE

CL

tn-1 (INPUT)

tn

(OUTPUT)

J

K

R

Qn-1

Qn

0X0

0

0

1X0

0

1

X0

0

1

0

1

0

0

Qn-1

Qn-1

Toggle

Mode

X1

0

1

1

X

X

0

Qn-1

Qn-1

X

XX

1

X

0