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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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OPA388 Fiches technique(PDF) 26 Page - Texas Instruments |
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OPA388 Fiches technique(HTML) 26 Page - Texas Instruments |
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26 / 45 page  N/C ±IN +IN V± V+ OUTPUT N/C N/C VS+ GND Ground (GND) plane on another layer VOUT VIN GND Run the input traces as far away from the supply lines as possible RF RG Place components close to device and to each other to reduce parasitic errors Use low-ESR, ceramic bypass capacitors Copyright © 2017, Texas Instruments Incorporated GND + VIN VOUT RG RF 26 OPA388, OPA2388, OPA4388 SBOS777C – DECEMBER 2016 – REVISED MAY 2019 www.ti.com Product Folder Links: OPA388 OPA2388 OPA4388 Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated 10 Layout 10.1 Layout Guidelines Paying attention to good layout practice is always recommended. Keep traces short and, when possible, use a printed-circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-µF capacitor closely across the supply pins. These guidelines must be applied throughout the analog circuit to improve performance and provide benefits such as reducing the electromagnetic interference (EMI) susceptibility. For lowest offset voltage and precision performance, circuit layout and mechanical conditions must be optimized. Avoid temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed from connecting dissimilar conductors. These thermally-generated potentials can be made to cancel by assuring they are equal on both input terminals. Other layout and design considerations include: • Use low thermoelectric-coefficient conditions (avoid dissimilar metals). • Thermally isolate components from power supplies or other heat sources. • Shield operational amplifier and input circuitry from air currents, such as cooling fans. Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause thermoelectric voltage drift of 0.1 µV/°C or higher, depending on materials used. 10.2 Layout Example Figure 49. Schematic Representation Figure 50. OPA388 Layout Example |
Numéro de pièce similaire - OPA388_V01 |
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Description similaire - OPA388_V01 |
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