Moteur de recherche de fiches techniques de composants électroniques |
|
MSP430FR6007 Fiches technique(PDF) 69 Page - Texas Instruments |
|
|
MSP430FR6007 Fiches technique(HTML) 69 Page - Texas Instruments |
69 / 179 page 69 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3 – MARCH 2020 Submit Documentation Feedback Product Folder Links: MSP430FR6007 MSP430FR6005 Specifications Copyright © 2020, Texas Instruments Incorporated Table 5-42 lists the characteristics of the USS bias voltage generator. Table 5-42. USS Bias Voltage Generator over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vexc_bias Excitation bias voltage (coupling capacitors) PVCC = VCC (2.2 V to 3.6 V) EXCBIAS = 0 200 mV EXCBIAS = 1 300 EXCBIAS = 2 400 EXCBIAS = 3 600 RVBE Impedance of excitation bias generator PVCC = VCC (2.2 V to 3.6 V) BIMP = 0 450 Ω BIMP = 1 850 BIMP = 2 1450 BIMP = 3 2900 tSBE Excitation bias settling time PVCC = VCC (2.2 V to 3.6 V), to 0.1% end value, RET = 200 Ω, CK + C0P = 1 nF, BIMP = 2 20 µs Vpga_bias PGA bias voltage (coupling capacitors) PVCC = VCC (2.2 V to 3.6 V) PGABIAS = 0 750 mV PGABIAS = 1 800 PGABIAS = 2 900 PGABIAS = 3 950 RVBA Impedance of acquisition bias generator PVCC = VCC (2.2 V to 3.6 V) BIMP = 0 500 Ω BIMP = 1 900 BIMP = 2 1500 BIMP = 3 2950 tSBA Acquisition bias settling time PVCC = VCC (2.2 V to 3.6 V), to 0.1% end value, RET = 200 Ω, CK + C0P = 1 nF, BIMP = 2 22 µs 5.13.15 Emulation and Debug Table 5-43 lists the characteristics of the JTAG and SBW interface. (1) Tools that access the Spy-Bi-Wire and the BSL interfaces must wait for the tSBW,En time after the first transition of the TEST/SBWTCK pin (low to high), before the second transition of the pin (high to low) during the entry sequence. (2) fTCK may be restricted to meet the timing requirements of the module selected. Table 5-43. JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC MIN TYP MAX UNIT IJTAG Supply current adder when JTAG active (but not clocked) 2.2 V, 3.0 V 40 100 μA fSBW Spy-Bi-Wire input frequency 2.2 V, 3.0 V 0 10 MHz tSBW,Low Spy-Bi-Wire low clock pulse duration 2.2 V, 3.0 V 0.04 15 μs tSBW, En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)(1) 2.2 V, 3.0 V 110 μs tSBW,Rst Spy-Bi-Wire return to normal operation time 15 100 μs fTCK TCK input frequency, 4-wire JTAG(2) 2.2 V 0 16 MHz 3.0 V 0 16 Rinternal Internal pulldown resistance on TEST 2.2 V, 3.0 V 20 35 50 k Ω fTCLK TCLK/MCLK frequency during JTAG access, no FRAM access (limited by fSYSTEM) 16 MHz tTCLK,Low/High TCLK low or high clock pulse duration, no FRAM access 25 ns fTCLK,FRAM TCLK/MCLK frequency during JTAG access, including FRAM access (limited by fSYSTEM with no FRAM wait states) 4 MHz tTCLK,FRAM, Low/High TCLK low or high clock pulse duration, including FRAM accesses 100 ns |
Numéro de pièce similaire - MSP430FR6007 |
|
Description similaire - MSP430FR6007 |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |