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MSP430F5310 Fiches technique(PDF) 44 Page - Texas Instruments |
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MSP430F5310 Fiches technique(HTML) 44 Page - Texas Instruments |
44 / 109 page 44 MSP430F5310, MSP430F5309, MSP430F5308, MSP430F5304 SLAS677G – SEPTEMBER 2010 – REVISED MAY 2020 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304 Detailed Description Copyright © 2010–2020, Texas Instruments Incorporated (1) Multiple source flags (2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space. (Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it. (3) Interrupt flags are in the module. (4) Only on devices with ADC, otherwise reserved. 6.3 Interrupt Vector Addresses The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 6-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 6-1. Interrupt Sources, Flags, and Vectors INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY System Reset Power up External reset Watchdog time-out, password violation Flash memory password violation WDTIFG, KEYV (SYSRSTIV) (1) (2) Reset 0FFFEh 63, highest System NMI PMM Vacant memory access JTAG mailbox SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV) (1) (Non)maskable 0FFFCh 62 User NMI NMI Oscillator fault Flash memory access violation NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV) (1) (2) (Non)maskable 0FFFAh 61 Comp_B Comparator B interrupt flags (CBIV) (1) (3) Maskable 0FFF8h 60 TB0 TB0CCR0 CCIFG0 (3) Maskable 0FFF6h 59 TB0 TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6, TB0IFG (TB0IV) (1) (3) Maskable 0FFF4h 58 Watchdog Timer_A interval timer mode WDTIFG Maskable 0FFF2h 57 USCI_A0 receive or transmit UCA0RXIFG, UCA0TXIFG (UCA0IV) (1) (3) Maskable 0FFF0h 56 USCI_B0 receive or transmit UCB0RXIFG, UCB0TXIFG (UCAB0IV) (1) (3) Maskable 0FFEEh 55 ADC10_A ADC10IFG0 (1) (3) (4) Maskable 0FFECh 54 TA0 TA0CCR0 CCIFG0 (3) Maskable 0FFEAh 53 TA0 TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4, TA0IFG (TA0IV) (1) (3) Maskable 0FFE8h 52 LDO-PWR LDOOFFIG, LDOONIFG, LDOOVLIFG Maskable 0FFE6h 51 DMA DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1) (3) Maskable 0FFE4h 50 TA1 TA1CCR0 CCIFG0 (3) Maskable 0FFE2h 49 TA1 TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2, TA1IFG (TA1IV) (1) (3) Maskable 0FFE0h 48 I/O port P1 P1IFG.0 to P1IFG.7 (P1IV) (1) (3) Maskable 0FFDEh 47 USCI_A1 receive or transmit UCA1RXIFG, UCA1TXIFG (UCA1IV) (1) (3) Maskable 0FFDCh 46 USCI_B1 receive or transmit UCB1RXIFG, UCB1TXIFG (UCB1IV) (1) (3) Maskable 0FFDAh 45 TA2 TA2CCR0 CCIFG0 (3) Maskable 0FFD8h 44 TA2 TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2, TA2IFG (TA2IV) (1) (3) Maskable 0FFD6h 43 I/O port P2 P2IFG.0 to P2IFG.7 (P2IV) (1) (3) Maskable 0FFD4h 42 RTC_A RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV) (1) (3) Maskable 0FFD2h 41 |
Numéro de pièce similaire - MSP430F5310_V01 |
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Description similaire - MSP430F5310_V01 |
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